Sep
4, 2007 (Rev 2.1s)
13/26
TB-5V-LX110/220/330-DDR2Hardware User Guide Rev2.1s
1
2
4
8
6
32
64
128
256
M0
M1
M2
M3
M4
M5
M6
M7
M8
250
0
1
0
1
1
1
1
1
0
1
0
0
0
251
1
1
0
1
1
1
1
1
0
1.5
1
0
0
252
0
0
1
1
1
1
1
1
0
2
0
1
0
253
1
0
1
1
1
1
1
1
0
3
1
1
0
*
*
*
*
*
*
*
*
*
*
4
0
0
1
*
*
*
*
*
*
*
*
*
*
6
1
0
1
*
*
*
*
*
*
*
*
*
*
8
0
1
1
500
0
0
1
0
1
1
1
1
1
12
1
1
1
N2
M
N
N0
N1
PLLIC (ICS8430-61) Setting
DIP switches SW5 to SW7 are used to set output frequency of PLLIC.
Output frequency can be obtained in the following formula.
Fout = (fxtal/16)x(M/N)
Be sure to set it so that internal VCO frequency fvco((fxtal/16)x M) is within a range of 250 - 500MHz.
*Ex) M=250/N=2 setting generates 125MHz clock. ===> Fout = 16/ 6x250/2 = 125MHz
Table.3 ICS8430-61 Setting
*Note: Value (“1” or “0”) of the setting
M0-M6, N0 and N2of DIP switches: When the setting of DIP switches are "ON", each value is
set to "1 (High)"
M7,M8 and N1 of DIP switches: When the setting of DIP switches are "ON", each value is set
to "0 (Low)"
See Table.4 DIP Switch Setting for relationship between DIP switch setting and PLL output frequency
when a 16MHz oscillator that comes with the board is used.
Table.4 DIP Switch Setting
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
N2
133
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
166
OFF
ON
OFF
OFF
ON
ON
ON
OFF
OFF
ON
OFF
OFF
200
OFF
OFF
ON
ON
OFF
ON
OFF
ON
OFF
ON
ON
OFF
266
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
333.33
OFF
OFF
ON
OFF
ON
ON
ON
OFF
OFF
ON
ON
OFF
SW7
Output freq.
(MH
ｚ
)
SW5
SW6
