Infineon ISOFACE ISO2H823V2, Manual

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Application Note 7 2015-02-11
Revision 1.0
ISO2H823V2.5 Evaluation Board
Board Manual
Functional Description
Figure 3 Bus Configuration for parallel mode
The timing requirements for the parallel interface are shown in
Figure 4
(Read),
Figure 5
(Write) and inside the
chapter electrical characteristics in the
ISO2H823V2.5
datasheet.
Figure 4 Timing by Parallel Read Access (e.g. GLERR Register)
For a reading access to internal registers the MSB of the address register has to be set to “0”.
V
CC
CS
WR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
MC
U
(e
.g
. X
M
C
xxxx)
or
ASI
C
IS
O2
H
82
3
V
2
parallel _interface_iso2h823.vsd
V
CC
ALE
SEL
RD
rd_timing_ifx - uc _parallel
CS
AD[7:0]
t
ADout
ALE
RD
t
AD_hd
t
RDlow
t
RDhigh
t
RD_su
t
float
t
RD_hd
t
clrrdy
00h
GLERR
GLERR address (04h) GLERR data
t
AD_su
GLERR data
t
CSD
t
CS_ALE
t
ALE_high