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Application Note 

23 

2011-07-06 

Q100

IPA60R199CP

Q102

IPA60R199CP

C106

33nF/630V

+

C107

0m47/16V

2

1

3

4

IC100

SFH617A-3

R101

10k

R119

11k

R120

3k01

R125

3k6

R116

560

R122

820

R117

3k9

2

3

1

IC101

TL431

+

C119

1u

C114 47n

C120

NC

12V

S_PGND

+

C100

270uF/450V

P_VBUS

P_PGND

+

C108

0m47/16V

+

C109

0m47/16V

+

C110

0m47/16V

RT100 5R

R124

NC

Q101

015N04

Q103

015N04

+

C111

0m47/16V

L100

40uH//RM10

R107

1R0

R110

10R

C102

33nF/630V

R100

10R

R105

10k

R104

10R

P_VCC

C105
100n/25V

+

C104
10u/25V

P_SGND

TR101

EE13

C103

2n2/Y1

Q107

BC546

Q104

BC546

Q106
BC557

Q105

BC557

R112

NC

R111

NC

R109

10R

C113

1u0

SGND

R108

10k

R102

1R0

R103

10k

R106

1k0

R114

430R

R115

430R

R113

1k0

D100

1N4148

D101

1N4148

ZD100

5V1

ZD101

5V1

R123

2k2

ZD102

9v1

C115

100p

C117

10n

R118

56R

TR100

PQ3230

C116

100n

C112

100n

R121

0R

P_VCC

P_SGND

P_HG

P_HS

P_PLG

P_PGND

P_VCr

P_SHG

P_SLG

S_LG

S_HG

P_Vreg

S_HD

S_HS

S_LD

S_LS

12V

12V

+ C121

10u

C122

100n

C118

1n0

INB

OUTB

OUTA

INA

GND

NC

VDD

NC

IC300

UCC27324_1

12V

S_LG

S_HG

 

Figure 13 

Power stage circuit of the half-bridge LLC converter 

P_VBUS

P_GND

P_VCC

P_LS

NC

P_LG

P_HS

P_Vreg

Reg GND

P_HG

NC

P_VCr

C201

100n

C210

1n0

C209

1u

R

214

1M0

C211
2.2u

Vres

VINS

CL

Vmc

Vref

TD

CS

SRD

GND

SHG

SLG

LG

SS

FREQ

LOAD

Delay

HG

VCC

Timer

EnA

IC201

C213

10n

C208

470p/1kV

R212

200R

R228

68R

C214

470n

D201
1N4148

D202

1N4148

R

213

1M0

R206 5k6/1%

R2

16

51

k/

1%

R2

17

NC

C212

NC

R2

18

33

k/

1%

R2

08

261k

R207 8k2/1%

P_Vreg

R205

0M2

R215

2M0

R21

9

NC

R

220 0R

R2

21

12

k

R2

22

6k

2

C207

100n

P_SHG

P_SLG

P_VCC

R209

154k/1%

R224

1M5/1%

R223

1M5/1%

R225

1M5/1%

R226

1M5/1%

R227

24k

P_VBUS

R211

154k/1%

R210

680k C206

47nF

P_

VC

r

C204

100n

P_HS

P_HG

NC

NC

P_SHG

P_SLG

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

J?

CON16R

C203
820p

C205
100n

C200

100n

GN

D

LV

G

H

V

G

HI

N

VC

C

L

IN

OU

T

Vb

oo

t

IC200

IC-ST-L6385

R200

10R

R201

11k

R202 10R

R203

11k

P_VCC

P_LG

 

Figure 14 

Control circuit of the half-bridge LLC converter 

Summary of Contents for ICE2HS01G

Page 1: ...N e v e r s t o p t h i n k i n g Power Management Supply Design Guide for LLC Converter with ICE2HS01G Application Note V1 0 July 2011...

Page 2: ...act your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contac...

Page 3: ...r LLC Converter with ICE2HS01 Revision History 2011 07 V1 0 Previous Version NA Design Guide for LLC Converter with ICE2HS01G License to Infineon Technologies Asia Pacific Pte Ltd A N P S 0 0 5 7 Liu...

Page 4: ...mum Maximum frequency setting 10 2 3 3 Frequency setting for OCP 11 2 3 4 Dead time 12 2 3 5 Softstart time OLP blanking time and auto restart time 13 2 3 6 Load pin setting 13 2 3 7 Current sense 13...

Page 5: ...th ICE2HS01G TL431 OPTO QPH CRES CO1 CO2 RBA1 RBA2 ROVS2 ROVS3 ROVS1 Roc Coc QPL CBUS RT CSS RFMIN Rreg ROCP RFT2 RFT1 RSS1 CSS1 QSH QSL IC Driver IC Driver Pulse Trans RINS1 RINS2 HG LG RINS3 VINS VC...

Page 6: ...minimum input voltage can be given as 2 2 2 2 Selection of resonant factor m In order to achieve the highest efficiency possible the value of resonant factor r r m r p L L L L L m is to be set as big...

Page 7: ...19 1 1 2 337 400 min _ _ max nom in nom in M V V M 3 2 2 4 Transformer turns ratio Assuming the drain source voltage drop of secondary side MOSFET V Vf 1 0 the transformer turns ratio will be 5 16 1 1...

Page 8: ...rQ we can calculate the r C r L and p L as follows nF R f Q C eff r r 66 106 10 85 268 0 2 1 2 1 3 8 uH C f L r r r 53 10 66 10 85 2 1 2 1 9 2 3 2 9 uH mL L r p 690 2 2 6 1 Resonant choke design The m...

Page 9: ...gain 28 1 pk G Accordingly the actual minimum frequency min f is kHz f F f r 30 10 85 35 0 3 min The voltage across the primary winding can be calculated as f o p V V n V The half switching cycle peri...

Page 10: ...quency setting The IC internal circuit provides a regulated 2V voltage at FREQ pin The effective resistance presented between the FREQ pin and GND determines the current flowing out of the FREQ pin wh...

Page 11: ...equation we get 0 1 1 min 2 2 Q M m F m F Q F G 15 The corresponding normalized frequency max F can be found by 13 2 1 1 min mM m F Therefore kHz kHz F f 180 85 max For 180 kHz switching frequency the...

Page 12: ...99CP at maximum switching frequency where the magnetizing current to charge and discharge ds C is the minimum The magnetizing current at the end of each switching cycle can be calculated as 18 The req...

Page 13: ...T BL T TH T T OLP 240 10 20 10 4 1 ln 10 10 1000 20 1 ln 20 6 6 6 6 The restart time can be calculated as ms V V C R T TH TL T T restart 2030 1000 4 525 0 ln 10 10 ln 6 6 2 3 6 Load pin setting One of...

Page 14: ...divider r cs ocp r cs cs ocp C C C I C C C I I cs 1 1 1 1 21 One major design criterion for the current sense is to ensure Over Current Protection OCP Accordingly we can also obtain 2 8 0 2 2 2 1 cs R...

Page 15: ...for INSL R is 24k The blanking time for leaving brown out is around 500 s and for entering brown out is around 50 s Please note that the calculation above is based on typical specification values of t...

Page 16: ...burst mode will be disabled After the selection is done the current source sele I is turned off A blanking time of 320 s is given before IC starts to sense the EnA pin voltage latch off enable purpos...

Page 17: ...the gate signals from IC to the actual MOSFET In this operation condition sw f r f the SR MOSFET conduction period on time depends on the primary gate switching frequency From Figure 7 right the curr...

Page 18: ...depends on the resonant frequency when LLC converter operates below resonant frequency sw f r f Considering the primary side dead time DEAD T and the SR gate turn on delay delay on T _ will be discus...

Page 19: ...pin 2V Therefore the SR on time in such conditions is determined by SRD R only and is equal to max _ on T In case of light load with low CS voltage CS V the CL V is reduced to be lower than 2V and ex...

Page 20: ...The turn on delay function is built in ICE2HS01G for such purpose When the sensed input voltage at VINS pin is higher than the reference voltage set by Vres pin according to the resonant voltage SR tu...

Page 21: ...turn off delay delay off T _ simplified typical waveforms can be drawn in Figure 12 for the two conditions when sw f r f and sw f r f From the waveforms on the left the switch on of the SR MOSFET is...

Page 22: ...9V SR is disabled SR will be enabled with SRSoftstart after CS pin voltage is lower than 0 6V All the above four conditions are built inside the IC If IC detects such a condition IC will disable SR an...

Page 23: ..._SLG S_LG S_HG P_Vreg S_HD S_HS S_LD S_LS 12V 12V C121 10u C122 100n C118 1n0 INB OUTB OUTA INA GND NC VDD NC IC300 UCC27324_1 12V S_LG S_HG Figure 13 Power stage circuit of the half bridge LLC conver...

Page 24: ...the red curves in the circuit diagram below 2 Connect driver IC input ground to IC VCC Ecap ground 3 Connect driver IC output ground to low side MOS source with short path 4 A 100nF filtering cap sho...

Page 25: ...resistor ground 2 Connetc the following ground with min F R ground refer to the green curves SS cap ground Opto coupler ground 3 Connect SR pulse transformer and driving circuit ground to VCC Ecap gro...

Page 26: ...n Note 26 2011 07 06 References 1 Infineon Technologies ICE2HS01 High Performance Resonant Mode Controller for Half bridge LLC Resonant Converter datasheet Ver 2 0 Infineon Technologies Munich Germany...

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