Application Note
19
2011-07-06
From Figure 9 below,
SRD
R
is selected to be 66k
Ω
to achieve
us
T
on
31
.
5
max
_
=
. Usually customer
should start with a smaller SR on time for safety and then adjust it to achieve higher efficiency.
Figure 9
SR on time versus SRD resistance
A simple constant on time control does not provide the best efficiency of LLC HB converter for the whole
load range. In fact, the actual resonant period of secondary current reduces when the output load
decreases or input voltage increases. The primary winding current can reflects this change. The current
sense circuit can be designed to get such information and input to CS pin. In ICE2HS01G, a function
called current level (CL) pin is implemented. During heavy load and low input voltage, the CL pin voltage
(
CL
V
)
is clamped at same voltage of SRD pin, 2V. Therefore, the SR on time in such conditions is
determined by
SRD
R
only
and is equal to
max
_
on
T
. In case of light load, with low CS voltage(
CS
V
), the
CL
V
is reduced to be lower than 2V and extra current will be drawn from SRD pin, thereby the actual SR
on time is reduced. The relationship between
CS
V
and
CL
V
is shown in Figure 10(top). The resistor
CL
R
can be adjusted to find the suitable reducing speed of SR on time for either better reliability or better
efficiency.
CL
R
is normally around 10 times
SRD
R
, which is 680k
Ω
in this design. Below is the detailed
calculation for the 300W design example:
We obtain the
CS
V
for full load condition, based on the circuit in Figure 5:
V
C
C
I
R
V
r
cs
rms
in
cs
cs
635
.
0
10
*
66
10
*
470
*
06
.
2
*
68
*
2
*
*
2
9
12
1
max
_
_
2
=
=
=
−
−
π
π
The corresponding
CL
V
is clamped at 2V according to Figure 10(top) and the SR on time is
max
_
on
T
.
Then for
CS
V
= 0.4V where
CL
V
is exactly 2V, the corresponding load is 63% of the full load, which is
around 16A output current(Figure 10, bottom).