Infineon Cypress F2MC-8FX Series, Operation Manual, Page: 36 / 40

MB2146-401 F
2
MC-8FX Family Evaluation Board Operation Guide, Doc. # 002-07324 Rev. *A 35
Specification
5.8 Circuit diagram
PWDATA[7:0]
[2,3]
BGOENX
[2]
PWDATA6
PC0
PRDATA[7:0]
[2,3]
NC1
[2]
P51
P65
LVR[4:0]
[2]
SEL[4:0]
[2]
AVcc3
[2]
PG0
[2
]
SEL2
PWDATA0
PB7
VCC
P66 PC6 P40 PEA3
P35 P43
P93
BSIN
[2]
P5[5:0]
[2
]
P73
P5[5:0]
[2]
P12 PRDATA6
PD6
PADDR3
PADDR2
PF[2:0]
[2
]
PEB6
LVR[4:0]
[2
]
PD3 PEA7
PRDATA[7:0]
[2,3]
ROMS0
[2]
P62
DA1
[2]
PCLK
[2,3]
P2A[7:0]
[2
]
P15
P76
PB3
PWRITE
[2,3]
PF1
P0B6
LVR1
P8[4:0]
[2
]
P2A[7:0]
[2]
P60
P52 P81
NC4
[2
]
AVR
[2,4]
PRDATA5
PC[7:0]
[2
]
M
O
D
[2]
P50
P61
PEB3
PA0
BEXCK
[2
]
PC1 P2A5 PB4
TCLK
[2]
P67
P44
RSTX
[2,3]
LVDENX
[2
]
PWDATA3
P72
CSVENX
[2
]
PA[3:0]
[2]
PEB1
PEB0
P92 PC2
BSOUT
[2
]
PEA0
PWDATA4
TESTO
[2
]
P11
LVR0
PC[7:0]
[2]
PC5
P90
P
A
C
T
IV
E
[2,3]
PSEL_EXT
[2,3]
P
IN
T
0
[2,3]
P2A0 P2A4
P0A0
P91
PRDATA[7:0]
[2,3]
PWDATA1
LVDREXT
[2
]
PD5 P0A1
P0C[7:0]
[2,3]
P9[5:0]
[2]
PEA6
P55
P80
PD1
PADDR1
P0C1
PB5
PADDR6
P2A3
PEA1
P47
ROMS1
[2
]
BRSTX
[2]
PD[7:0]
[2]
PWDATA[7:0]
[2,3]
PB[7:0]
[2]
P0C5
LVR2
PADDR[7:0]
[2,3]
P0B5
SEL3 P0A4
PEB7
PRDATA3
PB1
PC[7:0]
[2]
P0C[7:0]
[2,3]
P32 PEA5
APBENX
[2,3]
P0C7
CN1 WR-120SB-VF-1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98
100 102 104 106 108 110 112 114 116 118 120
PC4 PC2 PC0 PB5 PB7 PB0 PB3
P95
PA3
P90
PA1
GND_1
CSVENX
P92
LVCC
Cpin
LVDENX2
TESTO
LVR2 LVR1 LVR3
LVDREXT
LVDENX
GND_3
P20A P21A P24A P26A P24B P23B
P52 P54 P70 P73 P71 P80
GND_5
P75
PG0
P81
BSOUT
P83 X0A
ROMS1
Vss_2
BEXCK
MOD
X1A
GND_7
PINT0
PF1
NC2
APBENX
PCLK
PACTIVE
PWRITE
PADDR2 PADDR4 PADDR7 PADDR6
PC1 PC3 PB4 PB6 PB2 PB1 PA2 PA0 P94 P91 P93 GND_2 Vss_1 TCLK LVDIN Vcc51 LVR4 LVDOUT BGOENX LVR0 LVSS LVDBGR P22A GND_4 NC1 P23A P25A P27A P50 P51 P55 P53 P74 P72 P76 P77 GND_6 P82 P84 ROMS0 BDBMX BRSTX RSTX BSIN X0 X1 PF2 Vcc53 GND_8 PSEL_EXT PF0 PENABLE PINT1 PADDR0 PLOCK PADDR1 PADDR3 PADDR5 PRDATA0 PRDATA1
P0C6 P45
LVCC
[2,4]
PEB4 P0B3
P74
P2B3
PC[7:0]
[2
]
PA1
PA2
PC4
LVR4
PEB2 P0B2
PWDATA5
JP8
XJ8B-0211
1
2
X0A
[2
]
BDBMX
[2]
LVDIN
[2]
P36
P71
P0C2
P0A[7:0]
[2]
P94
P2A1
PWDATA7 PD4
P0B[7:0]
[2]
A
V
s
s
[2,4]
SEL0
PF0 P53
P0A2
PRDATA2
CN5
PCW-3-1-1PW
1
2
SEL1 P0B1
PADDR7
NC2
[2
]
P2A2
P1[6:0]
[2]
P7[7:0]
[2]
P0B7
P0A[7:0]
[2
]
P30
VCC
P41
PD[7:0]
[2
]
P3[7:0]
[2]
LVDENX2
[2
]
CN3
CAP-SOCKET
IC26-2010-GS4(2pin)
1 2
1 2
PLOCK
[2,3]
P0C3
PRDATA1
P4[7:0]
[2]
PB2 PF2
P34
PWDATA2
P0A5
P95 P54
PB[7:0]
[2
]
P16
PF[2:0]
[2]
PEA4
PD7
PC3
P1[6:0]
[2
]
P37
PEB5
PEA2
PEA[7:0]
[2
]
P64
P0B[7:0]
[2
]
SEL4 PRDATA7
PA3
PEB[7:0]
[2]
PB0 P2B4
P6[7:0]
[2,3]
P3[7:0]
[2
]
PEA[7:0]
[2]
PADDR[7:0]
[2,3]
X1A
[2
]
P0C4
P4[7:0]
[2
]
LVDBGR
[2]
P63
PINT1
[2,3]
P70
P0B4 P46
AVR3
[2
]
DA0
[2]
PENABLE
[2,3]
P9[5:0]
[2
]
PEB[7:0]
[2
]
NC3
[2
]
P7[7:0]
[2
]
Cpin
[2
]
X1
[2]
P2B[4:3]
[2
]
PADDR0 PADDR5
R8 4.7K
1
2
PRDATA4
P14 P0A6
PADDR4
CN2 WR-120SB-VF-1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98
100 102 104 106 108 110 112 114 116 118 120
PC5 PC6 PD1 PD3 PD5
P61
PD6
P66 P62
PE3A
P63
GND_1
PE4A PE1A PE7A PE6A PE2B PE1B PE6B PE5B
NC4
SEL3 SEL1
GND_3
P06C P05C P01C P03C P04A P06A P02A P01A P06B P04B P02B
P46
GND_5
P01B
P41 P45 P34 P44 P31 P40
AVss
P33
AVR3
AVcc
GND_7
P14 P16 P13 P11
NC3
PWDATA5 PWDATA4 PWDATA0 PWDATA2
PRDATA3 PRDATA5
PD0 PC7 PD2 PD4 PD7 P60 P64 P65 PE0A PE2A P67 GND_2 Vcc54 PE5A PE3B Vss PE7B PE0B SEL2 PE4B SEL0 SEL4 P04C GND_4 P07C P00C P02C P07A P05A P03A P07B P00A P05B P03B P00B P47 GND_6 P43 P42 P37 P35 P36 AVcc3 P32 AVR P30 P15 DA0 GND_8 P10 DA1 PWDATA7 P12 PWDATA3 PWDATA6 PRDATA7 PWDATA1 PRDATA6 PRDATA4 PRDATA2
SEL[4:0]
[2
]
PD2
PRDATA0
P6[7:0]
[2,3]
P0A3
P13 P33
P0C0 PC7
P77
P75
P31
P83 LVR3
P8[4:0]
[2]
P10
P2A6
VCC
P0A7
X0
[2]
PA[3:0]
[2
]
P42
P84 P82
RD1-TCO3Y9BD
ITF-SUWA
H.Hojo
14
H.Hojo
ITF-SUWA
-
2004-02-03
Date.
Title Document Number
Sect.
DR. CH.
APR.
Page
/
R
e
v
.
Zone
D
a
te
B
y
Sect.
P0B0
P2A7
LVSS
[2,4]
LVDOUT
[2]
PD0
PB6
A
V
c
c
[2,4]
CONNECTOR A
CONNECTOR B
F2MC-8FX ADAPTER BOARD INTERFACE
F2MC-8FX Standard evaluation Board Assy
JP Name display
[MOD]
Incorrect insertion preventive measures
CN name silk display
[Cap.]