User Guide
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002-34554 Rev. *A
2022-08-01
CY-SD4210 EZ-
USB™ SX3 HDMI 4K capture
kit guide
EZ-
USB™ SX3 HDMI 4K capture kit system design
3.2.3
Power supply
The kit consists of five DC-DC step-down regulators with ratings as listed below. AP3428KTTR-G1 from Diodes
Inc. is used due to its small form factor. All voltages listed below are generated from VBUS (i.e., 5 V ± 0.25 V).
•
U1: 3.3 V ±5% at 1A
•
U2: 2.5 V ± 5% at 1A
•
U3: 1.5 V ± 5% at 1A
•
U4: 1.2 V ± 5% at 1A
•
U8: 1.1 V ± 5% at 1A
The kit also uses a 2A DDR termination controller (U9) to power the VTT bus terminations. It also provides the
reference output to the DDR IC.
3.2.4
SX3 (U6)
This is a USB 3.0 configurable SuperSpeed controller with a 32-bit ARM926EJ core CPU and 512 kB embedded
SRAM. It supports UVC, UAC, and USB vendor class protocols. With a general configurable interface of 8-, 16-, 24-
and 32-bit data bus at 100 MHz, SX3 supports slave FIFO and parallel camera interface features. It has dedicated
interfaces for SPI flash and I
2
C. SX3 supports selectable clock input frequencies at 19.2, 26, 38.4 and 52 MHz.
Additionally, a dedicated 19.2 MHz crystal input support is also available.
3.2.5
SPI flash (U11)
The kit configuration is stored on an Infineon Technologies 64-Mb SPI flash. After power-on, SX3 fetches the
required details from the configuration image, stores it in its RAM and starts executing from it.
3.2.6
HDMI connector (J6)
The kit has an onboard HDMI connector that allows it to connect to an external HDMI source using an HDMI cable.
3.2.7
Crystal (Y1, Y3)
Y1 is a 19.2 MHz crystal used by SX3 to generate the clock for its operation. Y3 is a 27 MHz crystal used by HDMI
RX.
3.2.8
LED (LED1)
LED1 (user LED) is a green LED connected to GPIO_4 of SX3. By default, with power-on, this LED glows green,
indicating the power to the kit. It can also be controlled by the application.
3.2.9
HDMI receiver (U17)
The kit uses a single-port HDMI receiver that supports HDMI 1.4b. It supports streaming of 4K videos with 24-bit
RGB digital video standard and up to four channels of I
2
S output.
3.2.10
Lattice ECP5 FPGA (U10)
The kit uses an ECP5 family FPGA from Lattice Semiconductor. It is a high-performance device with dedicated
DDR3 RAM interfaces and supports high-speed signaling. This FPGA acts as a bridge between the HDMI receiver
and the SX3 device. It receives 24-bit RGB video signals and I
2
S audio signals from the HDMI receiver, processes
and sends them to SX3 via the 32-bit slave FIFO interface at 100 MHz. This allows SX3 to directly communicate
with an HDMI source.
