On-Chip Peripheral Components
C513AO
User’s Manual
6-48
05.99
When the SSC is enabled for operation in Master Mode, pins P1.3/SRI, P1.4/STO, and P1.2/SCLK
will be switched to the SSC control function; P1.4/STO and P1.2/SCLK actively will drive the lines;
and P1.5/SLS will remain as a regular I/O pin.
Note: The output latches of port pins which are dedicated to alternate functions must be
programmed to logic 1 (= state after reset).
In Slave Mode, all four control pins will be switched to the alternate function. However, STO will stay
in tristate until the transmitter is enabled by the SLS input being low and the TEN control bit is set
to “1”. This allows more than one slave to be connected to one select line. The final selection of the
slave will be done by a software protocol.
6.4.3 Baudrate Generation (Master Mode only)
The baudrate clock is generated from the processor clock (
f
osc
÷ 2). This clock is fed into a resetable
divider with seven outputs for different baudrate clocks (
f
osc
/8 to
f
osc
/512). One of these eight clocks
is selected by the bits BRS2,1,0 in SSCCON and provided to the shift control logic.
Whenever the shift register is loaded with a new value, the baudrate generation is restarted with the
trailing edge of the write signal to the shift register. In the case of CPHA = 0, the baudrate generator
will be restarted in such a way that the first SCLK clock transition will not occur before one half the
transmit clock cycle time after the register load. This ensures that there is sufficient setup time
between MSB or LSB valid on the data output and the first sample clock edge; and ensures that the
MSB or LSB has the same length as the other bits (No special care is necessary in case of
CPHA = 1, because the first clock edge will be used for shifting).
6.4.4 Write Collision Detection
When an attempt is made to write data to the shift register while a transfer is in progress, the WCOL
bit in the status register will be set. The transfer in progress continues uninterrupted. The write will
not access the shift register and will not corrupt data. However, the data written erroneously will be
stored in a shadow register and can be read from the STB register.
There are different definitions for a transfer to be considered “in progress”. The definition depends
on the operating mode:
Master Mode:
CPHA = 0: from the trailing edge of the write into STB until the last sample clock edge
CPHA = 1: from the first SCLK clock edge until the last sample clock edge
Note: This also means that writing new data into STB immediately after the transfer complete flag
has been set (also initiated with the last sample clock edge) will not generate a write collision.
However, this may shorten the length of the last bit (especially at slow baudrates) and prevent
STO from switching to the forced “1” between transmissions.
Slave Mode:
CPHA = 0: while SLS is active
CPHA = 1: from the first SCLK clock edge until the last sample clock edge
