User’s Manual
6-47
05.99
On-Chip Peripheral Components
C513AO
Because the SSC is a synchronous serial interface, a dedicated clock signal sequence must be
provided for each transfer. The SSC has implemented a clock control circuit, which can generate
the clock via a baudrate generator in Master Mode, or receive the transfer clock in Slave Mode.
The clock signal is fully programmable for clock polarity and phase. The pin used for the clock
signal is P1.2/SCLK.
When operating in Slave Mode, a slave select input SLS enables the SSC interface and also
controls the transmitter output. The pin used for this is P1.5/SLS. There is an additional option to
control the transmitter output by software.
The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.
6.4.1 General Operation of the SSC
After initialization of the SSC, the data to be transmitted must be written into the shift register STB.
In Master Mode, this will initiate the transfer by resetting the baudrate generator and starting the
clock generation. The control bits CPOL and CPHA in the SSCCON register determine the idle
polarity of the clock (polarity between transfers) and which clock edges are used for shifting and
sampling data (see Figure 6-29).
While the transmit data in the shift register is shifted out bit-by-bit (starting with either the MSB or
LSB), the incoming receive data are shifted in. The shifting of transmit and receive data is
synchronized with the clock signal at pin SCLK. When the eight bits are shifted out (and an equal
number are shifted in), the contents of the shift register are transferred to the receive buffer register
SRB, and the Transmission Complete flag TC is set. If enabled, an interrupt request will be
generated.
After the last bit has been shifted out and has been stable for one bit time, the STO output will be
switched to “1” (forced “1”), the idle state of STO. This allows connection of standard asynchronous
receivers to the SSC in Master Mode.
In Slave Mode, the device will wait for the slave select input SLS to be activated (= low) and then
will shift in the data provided on the receive input according to the clock provided at the SCLK input
and the setting of the CPOL and CPHA bits. After eight bits have been shifted in, the contents of
the shift register are transferred to the receive buffer register and the transmission complete flag TC
is set. At the same time, if the transmitter is enabled in Slave Mode (TEN bit set to 1), the SSC will
shift out at STO the data currently contained in the shift register. If the transmitter is disabled, the
STO output will remain in the Tristate state. This allows more than one slave to share a common
select line.
If SLS is inactive, the SSC will be inactive and the contents of the shift register will not be modified.
6.4.2 Enable/Disable Control
Bit SSCEN of the SSCCON register globally enables or disables the Synchronous Serial Interface.
Setting SSCEN to “0” stops the baudrate generator and all internal activities of the SSC. Current
transfers are aborted. The alternate output functions at pins P1.3/SRI, P1.4/STO, P1.5/SLS, and
P1.2/SCLK return to their primary I/O port function. These pins can now be used for general
purpose I/O.
