User’s Manual
6-19
05.99
On-Chip Peripheral Components
C513AO
6.2.1.2 Mode 0
Putting either Timer/Counter 0 or Timer/Counter 1 into Mode 0 configures it as an 8-bit timer/
counter with a divide-by-32 prescaler. Figure 6-12 shows Mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all “1”s
to all “0”s, it sets the Timer overflow Flag, TF0. TF0 then can be used to request an interrupt. The
counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting
Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse-width
measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD.
The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0
are indeterminate and should be ignored. Setting the Run flag (TR0) does not clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer 1. Substitute TR0, TF0, TH0, TL0 and INT0
for the corresponding Timer 1 signals shown in Figure 6-12. There are, however, two different gate
bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Figure 6-12
Timer/Counter 0, Mode 0: 13-Bit Timer/Counter
MCS02583
1
&
OSC
C/T = 0
TL0
TH0
TF0
C/T = 1
TR0
Gate
P3.2/INT0
Control
Interrupt
P3.4/T0
(5
÷ 12
=1
Bits)
Bits)
(8
_
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