Reset / System Clock
C513AO
User’s Manual
5-5
05.99
5.3
Hardware Reset Timing
This section describes the timing of the hardware reset signal.
The input pin RESET is sampled once during each machine cycle. This occurs in State 5 Phase 2
(S5P2). Thus, the external reset signal is synchronized to the internal CPU timing. When the
RESET signal is detected to be active at S5P2, the internal reset procedure is started. It needs two
complete machine cycles to put the complete device into its correct reset state; that is, all special
function registers contain their default values, the port latches contain “1”s, etc. Note that this reset
procedure is also performed if there is no clock available at the device. (This is done by the
Oscillator Watchdog, which provides an auxiliary clock for performing a perfect reset without clock
at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least two machine cycles;
after this interval, the C513AO remains in its reset state as long as the signal is active. When the
signal goes inactive, this transition is recognized in the subsequent S5P2 of the machine cycle.
Then, the processor starts its address output (when configured for external ROM) in the subsequent
State 5 Phase 1. One phase later (State 5, Phase 2), the first falling edge at pin ALE occurs.
Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus,
between the release of the RESET signal and the first falling edge at ALE there is a time interval of
at least one machine cycle but less than two machine cycles.
Figure 5-3
CPU Timing after Reset
MCT02092
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
P1 P2
PCL
OUT
PCH
OUT
PCH
OUT
One Machine Cycle
RESET
P0
P2
ALE
Inst.
in
OUT
PCL
