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OTP Memory Operation

C513AO-2E Only

User’s Manual

10-8

05.99

Basic Programming Mode is selected by executing the following steps:

1. With a stable V

DD

, a clock signal is applied to the XTAL pins; the RESET pin is set to “1” level

and the PSEN pin is set to “0” level.

2. PROG, PALE, PMSEL1, and EA/

V

PP

are set to “0” level; PRD, PSEL, and PMSEL0 are set to “1”

level.

3. PSEL is changed from “1” to “0” level and thereafter PROG is switched to “1” level.
4. PMSEL1,0 can now be changed; after EA/V

PP

has been set to

V

IH

high level or to

V

PP

, the OTP

memory is ready for access.

The pins RESET and PSEN must stay at “1” and “0” static signal levels respectively throughout
Programming Mode. With a falling edge of PSEL, the logic states of PROG and EA/

V

PP

are

internally latched. These two signals are now used as a programming write pulse signal (PROG)
and as a programming voltage input pin

V

PP

. After the falling edge of PSEL, PSEL must stay at “0”

state during all programming operations.

Note: If Protection Level 1 to 3 has been programmed (see Section 10.6 ) and Programming Mode

has been left, it is not possible to re-enter Programming Mode.

10.4.2 OTP Memory Access Mode Selection

When the C513AO-2E has been put into Programming Mode using basic programming mode
selection, several Access Modes of the OTP memory programming interface are available. The
conditions for the different control signals of these access modes are listed in Table 10-2.

The Access Modes from the table above are basically selected by setting the two PMSEL1,0 lines
to the required logic level. The PROG and PRD signals are the write and read strobe signals. Data
is transferred via Port 0 and addresses are applied to Port 2.

The following sections describe the details of the different Access Modes.

Table 10-2
Access Modes Selection

Access Mode

EA/

V

PP

PROG

PRD

PMSEL

Address

(Port 2)

Data

(Port 0)

1

0

Program OTP memory byte

V

PP

H

H

H

A0-7

A8-13

D0-7

Read OTP memory byte

V

IH

H

Program OTP lock bits

V

PP

H

H

L

–

D1,D0 see

Read OTP lock bits

V

IH

H

Read OTP version byte

V

IH

H

L

H

Byte addr.

of version byte

D0-7

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Summary of Contents for C513AO

Page 1: ...Microcomputer Components 8 bit CMOS Microcontroller C513AO User s Manual 05 99 DS 1 t t p w w w i n f i n e o n c o m...

Page 2: ...ineon Technologies Office in Germany or our Infineon Technolo gies Representatives worldwide see ad dress list Warnings Due to technical requirements components may contain dangerous substances For in...

Page 3: ...99 Previous Releases Page Subjects We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve t...

Page 4: ...g 4 3 4 1 3 External Program Memory Access 4 3 4 2 PSEN Program Store Enable 4 3 4 3 Overlapping External Data and Program Memory Spaces 4 3 4 3 1 Address Latch Enable ALE 4 4 4 4 Enhanced Hooks Emula...

Page 5: ...e Collision Detection 6 48 6 4 5 Master Slave Mode Selection 6 49 6 4 6 Data Clock Timing Relationships 6 50 6 4 6 1 Master Mode Operation 6 50 6 4 6 2 Slave Mode Operation 6 51 6 4 7 Register Descrip...

Page 6: ...nfiguration 10 1 10 2 Pin Configuration 10 2 10 3 OTP Programming Mode Pin Definitions 10 5 10 4 OTP Programming Mode Selection 10 7 10 4 1 Basic Programming Mode Selection 10 7 10 4 2 OTP Memory Acce...

Page 7: ...nchronous interface versatile fail safe and power saving mechanisms The C513AO 2E is the One Time Programmable OTP version of the C513AO microcontroller with a 16Kx8 OTP memory The C513AO L is the ver...

Page 8: ...16 bit auto reload features Full duplex serial interface USART Synchronous Serial Channel SSC Seven interrupt sources with two priority levels On chip emulation support logic Enhanced Hooks Emulation...

Page 9: ...al 1 3 05 99 Introduction C513AO Figure 1 2 Logic Symbol MCL04007 C513AO Port 0 8 Bit Digital I O Port 1 8 Bit Digital I O Port 2 8 Bit Digital I O Port 3 8 Bit Digital I O XTAL1 XTAL2 RESET EA ALE PS...

Page 10: ...P0 0 AD0 38 P0 1 AD1 37 P0 2 AD2 36 P0 3 AD3 35 P0 4 AD4 34 P0 5 AD5 33 P0 6 AD6 32 P0 7 AD7 EA 31 ALE 30 PSEN 29 28 27 P2 7 A15 P2 6 A14 26 P2 5 A13 P2 4 A12 25 P2 3 A11 24 P2 2 A10 23 P2 1 A9 22 P2...

Page 11: ...V SS XTAL1 XTAL2 P3 7 RD P3 6 WR P3 5 T1 17 P3 4 T0 16 P3 3 INT1 15 P3 2 INT0 14 P3 1 TxD 13 N C 12 P3 0 RxD 11 RESET 10 P1 7 9 P1 6 8 P1 5 SLS 7 40 41 42 43 44 1 2 3 4 5 6 P0 3 AD3 P0 2 AD2 P0 1 AD1...

Page 12: ...14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 VDD VSS XTAL1 XTAL2 P3 7 RD P3 6 WR P3 5 T1 P3 4 T0 P3 3 INT1 P3 2 INT0 P3 1 TxD N C P3 0 RxD RESET P1 7 P1 6 P1 5 SLS P1 4 STO P1 3 SRI P1 2 SCL...

Page 13: ...current IIL in the DC characteristics because of the internal pull up transistors The output latch corresponding to a secondary function must be programmed to a 1 for that function to operate For the...

Page 14: ...programmed to a 1 for that function to operate except for TxD and WR The secondary functions are assigned to the pins of Port 3 as follows P3 0 RxD Receiver data input asynch or data input output sync...

Page 15: ...specified in the AC characteristics must be observed P2 0 P2 7 21 28 24 31 18 25 I O Port 2 Port 2 is a an 8 bit quasi bidirectional I O port with internal pull up arrangement Port 2 pins that have 1...

Page 16: ...hould not be driven during reset operation EA 31 35 29 I External Access Enable When held at high level instructions are fetched from the internal program memory when the PC is less than 4000H When he...

Page 17: ...optimized EMC performance VDD 40 44 38 Power Supply 5 V 23 17 Ground 0 V Optional This pin may be left unconnected It is however recommended to connect this pin to VDD for optimized EMC performance N...

Page 18: ...AM are important features of the C513AO not found in the C501 Figure 2 1 illustrates the major blocks of the C513AO device Figure 2 1 Block Diagram of the C513AO MCB04011 Oscillator Watchdog OSC Timin...

Page 19: ...es and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and co...

Page 20: ...ack to begin at location 08H above Register Bank 0 The SP can be read or written by software Bit Function CY Carry Flag Used by arithmetic instruction AC Auxiliary Carry Flag Used by instructions whic...

Page 21: ...on begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If it is a one byte instr...

Page 22: ...Fundamental Structure C513AO User s Manual 2 5 05 99 Figure 2 2 Fetch Execute Sequence...

Page 23: ...bytes of internal data memory 256 bytes of internal XRAM data memory One 128 byte special function register area Figure 3 1 illustrates the memory address spaces of the C513AO Figure 3 1 C513AO Memor...

Page 24: ...of RAM can be accessed through register indirect addressing The special function registers are accessible through direct addressing Four 8 register banks each consisting of eight 8 bit general purpos...

Page 25: ...he cycle in which the active reset signal is detected MOVX is a 2 cycle instruction Reset during 1st cycle The new value will not be written to XRAM The old value is not affected Reset during 2nd cycl...

Page 26: ...sing these instructions with the XRAM disabled implies that Port 0 is used as the address data bus Port 2 is used for high address output and two lines of Port 3 P3 6 WR P3 7 RD are used for control N...

Page 27: ...ction Registers SFRs in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on chip peripherals The SFRs of the C513AO are listed in...

Page 28: ...CCON STB SRB SCF SCIEN SSCMOD8 SSC Control Register SSC Transmit Register SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register E8H 1 E9H EAH F8H 1 F9H EBH 07H XX...

Page 29: ...XXXXB 3 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is unde...

Page 30: ...FFH SLS STO SRI SCLK T2EX T2 98H 2 SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI 99H SBUF XXH 7 6 5 4 3 2 1 0 A0H 2 P2 FFH 7 6 5 4 3 2 1 0 A8H 2 IE 00H EA ESSC ET2 ES ET1 EX1 ET0 EX0 B0H 2 P3 FFH RD WR T1 T0...

Page 31: ...C5H 7 6 5 4 3 2 1 0 FDH 3 4 VR1 7 7 6 5 4 3 2 1 0 FEH 3 4 VR2 5 7 6 5 4 3 2 1 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is...

Page 32: ...ta Address Bus When used for accessing external memory Port 0 provides the data byte time multiplexed with the low byte of the address In this state Port 0 is disconnected from its own port latch and...

Page 33: ...PCL OUT valid PCL OUT valid ALE PSEN RD P2 a b P2 RD PSEN ALE valid PCL OUT valid PCL OUT MOVX with B IN DATA IN INST INST IN DPH OUT OR P2 OUT One Machine Cycle One Machine Cycle S6 S5 S4 S3 S2 S1 S6...

Page 34: ...SFR depending on whether the external data memory access is a MOVX DPTR or a MOVX Ri Since the C513AO L has no internal program memory accesses to program memory are always external and Port 2 is dedi...

Page 35: ...reduce system RFI Because ALE can be enabled disabled dynamically it is also possible to enable ALE only when external memory is accessed This can be useful if the external memory is accessed only rar...

Page 36: ...n EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is a...

Page 37: ...ed internally and the expected data bytes must be applied externally to the device by the manufacturer or by the customer and are compared internally with the data bytes from the ROM After 16 byte ver...

Page 38: ...dress 0002H 16 Data Byte content of internal ROM OTP address 000FH The C513AO does not output any address information during ROM OTP Verification Mode 2 The first data byte to be verified is always th...

Page 39: ...ess counter This counter generates the addresses for an external EPROM which is programmed with the content of the internal protected ROM OTP The verify detect logic typically displays the state of th...

Page 40: ...se rejection Since the reset is synchronized internally the RESET pin must be held high for at least two machine cycles 24 oscillator periods while the oscillator is running With the oscillator runnin...

Page 41: ...ycles have passed before the reset signal goes inactive Figure 5 1 Reset Circuitries A correct reset leaves the processor in a defined state The program execution starts at location 0000H After reset...

Page 42: ...1 s measured from VDD 4 25 V up to stable port condition the delay between power on and the correct port reset state is Typical 18 s Maximum 34 s The RC oscillator will already run at a VDD below 4 25...

Page 43: ...13AO V IV III II I Ports Undef Reset On Chip Osc RC Osc DD V Reset max 34 typ 18 undef Ports Clock from RC Oscillator Reset at Ports s Power On s Start of Program Execution Sequence On Chip Final Rese...

Page 44: ...xiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins The RESET signal must be active for at least two machine cycles after this interval the C513AO remains in its res...

Page 45: ...trolled positive reactance oscillator a more detailed schematic is given in Figure 5 5 lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor ex...

Page 46: ...ure 5 6 XTAL2 must be left unconnected A pull up resistor is suggested to increase the noise margin but is optional if VOH of the driving gate corresponds to the VIH3 specification of XTAL1 Figure 5 6...

Page 47: ...he Port 2 pins continue to emit the P2 SFR contents In this case Port 0 is not an open drain port but uses a strong internal pull up Field Effect Transistors FETs Port 1 pins used for Synchronous Seri...

Page 48: ...Ports 1 2 and 3 the pin is pulled high by the internal pull ups but can be pulled low by an external source When externally pulled low the port pins source current IIL or ITL For this reason these por...

Page 49: ...e pull up FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pull up FET sources a much lower current than p1 Therefore th...

Page 50: ...oltage level at the pin above p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 IIL the pin might remain in th...

Page 51: ...d Enable Push pull will be inactive and Tristate will be active Pin Control for SCO When the SSC is disabled both Enable Push pull and Tristate will be inactive In Master Mode with SSC enabled Enable...

Page 52: ...ed for the SSC will be switched into high impedance mode For P1 3 SRI Tristate will be enabled when the SSC is enabled For P1 5 SLS Tristate will be enabled when the SSC is enabled and is switched to...

Page 53: ...1 s during the external memory accesses Otherwise the pull up is always off Consequently P0 lines that are used as output port lines are open drain lines Writing a 1 to the port latch leaves both out...

Page 54: ...t level at the EA pin and or the contents of the program counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the P2 SF...

Page 55: ...the output pin and vice versa the gate between the latch and the driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR must contai...

Page 56: ...SSC inputs Figure 6 10 Port Pins P1 2 and P1 4 when used as SSC outputs MCS02435 D CLK Bit Latch Alternate Input Function Int Bus Write to Pin Read Latch Latch Read Port Pin Q Q MCS02436 D CLK Bit La...

Page 57: ...clock input P1 3 SRI SSC serial data in P1 4 STO SSC serial data out P1 5 SLS SSC slave select P3 0 RXD Serial port s receiver data input asynchronous or data input output P3 1 TXD Serial port s trans...

Page 58: ...s actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 6 11 illustrates this port timing It must be noted that this mechanism of sampling once per machine cy...

Page 59: ...he output buffers of Port 0 can also drive TTL inputs directly They do however require external pull ups to drive floating inputs except when used as the address data bus It must be noted that when us...

Page 60: ...k to the latch Read modify write instructions are directed to the latch rather than the pin to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used t...

Page 61: ...ignal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle 6 2 1 Timer Counter 0 and 1 Timer Counter 0 and Timer Counter 1 of...

Page 62: ...DH Reset Value 00H Bit Function TLx 7 0 x 0 1 Timer Counter 0 1 Low Register THx 7 0 x 0 1 Timer Counter 0 1 High Register 7 6 5 4 8AH TL0 Bit No 7 6 5 4 3 2 1 0 MSB LSB 3 2 1 0 7 6 5 4 8CH TH0 3 2 1...

Page 63: ...counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 Run control bit Set cleared by software to turn timer counter 1 ON OFF TF1 Timer 1 overflow Flag Set by ha...

Page 64: ...ut from internal system clock M1 M0 Mode select bits GATE C T M1 M0 89H TMOD Bit No 7 6 5 4 3 2 1 0 MSB LSB GATE C T M1 M0 Timer 1 Control Timer 0 Control M1 M0 Function 0 0 8 bit timer counter THx op...

Page 65: ...to be controlled by external input INT0 to facilitate pulse width measurements TR0 is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of...

Page 66: ...ode 1 is the same as Mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in Figure 6 13 Figure 6 13 Timer Counter 0 Mode 1 16 Bit Timer Counter MCS02095 1 OSC C T 0 TL0 T...

Page 67: ...imer register as an 8 bit counter TL0 with automatic reload as shown in Figure 6 14 Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents of TH0 which is preset by software The re...

Page 68: ...chine cycles and takes over TR1 and TF1 from Timer 1 Thus TH0 now controls the Timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When Timer 0 is in Mode 3...

Page 69: ...incremented in response to a 1 to 0 transition at its corresponding external input pin T2 P1 0 In this function the external input is sampled during S5P2 of every machine cycle When the samples show...

Page 70: ...e 00H Special Function Register RC2H Address CBH Reset Value 00H Bit Function TL2 7 0 Timer 2 value low byte The TL2 register holds the 8 bit low part of the 16 bit Timer 2 count value TH2 7 0 Timer 2...

Page 71: ...auses the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 TCLK 0 causes Timer 1 overflow to be used for the transmit clock EXEN2 Timer 2 External Enable...

Page 72: ...ture is invoked by a bit named DCEN Down Counter Enable SFR T2MOD 0C9H When DCEN is set Timer 2 can count up or down depending on the value of pin T2EX P1 1 Figure 6 16 shows Timer 2 automatically cou...

Page 73: ...e If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at the external input T2EX P1 1 This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can gene...

Page 74: ...stored in RC2H and RC2L The underflow sets the TF2 bit and causes FFFFH to be reloaded into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows This bit can be used as a...

Page 75: ...n at external input T2EX causes the current value in TH2 and TL2 to be captured into RC2H and RC2L respectively Additionally a transition at T2EX causes bit EXF2 in SFR T2CON to be set The EXF2 bit li...

Page 76: ...data bit and a stop bit 1 On transmit the 9th data bit TB8 in SCON can be assigned to the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit...

Page 77: ...by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte to determine if it is being addressed The addressed slave will clear its SM2 bit and...

Page 78: ...d RB8 Serial port Receiver Bit 9 In Modes 2 and 3 RB8 is the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used TI Serial port tRansmitte...

Page 79: ...baudrate generation is further controlled by bit SMOD which is located in SFR PCON Special Function Register PCON Address 87H Reset Value 0XX00000B Mode 0 The baudrate in Mode 0 is fixed Mode 0 baudr...

Page 80: ...rial Channel Figure 6 19 shows the configuration for the baudrate generation for the serial channel MCS04017 SCON 7 SCON 6 SM0 SM1 Mode 1 Mode 3 Mode 2 Mode 0 6 fOSC 2 Timer 1 Overflow Only one mode c...

Page 81: ...10B In that case the baudrate is given by the formula Modes 1 and 3 baudrate 2SMOD 32 fOSC 12 256 TH1 One can achieve very low baudrates with Timer 1 by leaving the Timer 1 interrupt enabled and confi...

Page 82: ...egisters to be reloaded with the 16 bit value in registers RC2H and RC2L which are preset by software The baudrates in Modes 1 and 3 are determined by the overflow rate of Timer 2 as follows Modes 1 a...

Page 83: ...ine cycle will elapse between WRITE to SBUF and activation of SEND SEND enables output of the shift register to the alternate output function line of P3 0 and enables SHIFT CLOCK to the alternate outp...

Page 84: ...ector D S CLK Q Shift Send 1 TX Control Start TX Clock TI RX Control Start RI Receive Shift Serial Port Interrupt Input Shift Register SBUF Internal Bus Write to SBUF Shift Load SBUF Read SBUF RXD P3...

Page 85: ...6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S D0 D1 D2 D3 D4 D5 D6 D7 ALE Write...

Page 86: ...is occurs at the 10th divide by 16 rollover after WRITE to SBUF Reception is initiated by a detected 1 to 0 transition at RXD For this purpose RXD is sampled at a rate of sixteen times whatever baudra...

Page 87: ...Internal Bus 1 SBUF Zero Detector D S CLK Q Data Send 1 to 0 Transition Detector TX Control Shift Start TX Clock RX Control Start Load Shift SBUF Sample Bit Detector 9Bits Input Shift Register 1FF SBU...

Page 88: ...re 6 24 Serial Interface Mode 1 Timing Diagram MCT02104 to SBUF D7 Stop Bit D6 D5 D4 D3 D2 D1 D0 Start Bit TI TXD Shift Data S1P1 Send D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Stop Bit 16 Reset Receive Trans...

Page 89: ...in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain 0 s This condition flags the TX con...

Page 90: ...us TB8 SBUF Zero Detector D S CLK Q Data Send 1 to 0 Transition Detector 1 16 TX Control Shift Start TX Clock TI RX Control Start RI Load Shift SBUF RX Clock Serial Port Interrupt Sample Bit Detector...

Page 91: ...e Mode 2 and 3 Timing Diagram MCT02587 Write to SBUF TX Clock D7 TB8 Stop Bit D6 D5 D4 D3 D2 D1 D0 Start Bit Stop Bit Gen TI TXD Shift Data Mode 2 S6P1 Send RX Clock RX D0 Start Bit D1 D2 D3 D4 D5 D6...

Page 92: ...tion and can run in Master Mode or Slave Mode Figure 6 27 shows the block diagram of the SSC The central element of the SSC is an 8 bit shift register The input and the output of this shift register a...

Page 93: ...he clock signal at pin SCLK When the eight bits are shifted out and an equal number are shifted in the contents of the shift register are transferred to the receive buffer register SRB and the Transmi...

Page 94: ...CLK clock transition will not occur before one half the transmit clock cycle time after the register load This ensures that there is sufficient setup time between MSB or LSB valid on the data output a...

Page 95: ...e The SSC has no on chip support for multi master configurations switching between Master and Slave Mode operation The SSC can operate as a master in a multi master environment if external circuitry i...

Page 96: ...ll sample with the next clock edge The direction rising or falling of the respective clock edge depends on the clock polarity selected After the last bit has been shifted out the data output STO will...

Page 97: ...with the first clock edge and the transmitter will shift out the next bit with the following clock edge If the transmitter is disabled the output will remain in the high impedance state In this case...

Page 98: ...H F8H E9H EAH EBH Bit Function SCEN SSC system Enable SCEN 0 SSC subsystem is disabled related pins are available as general I O SCEN 1 SSC subsystem is enabled TEN Slave Mode Transmitter Enable TEN 0...

Page 99: ...STO In Master Mode the transmitter will provide the first data bit on STO immediately after the data was written into the STB register In Slave Mode the transmitter if enabled via TEN will shift out t...

Page 100: ...by bit ESSC in the Interrupt Enable Register IE and by bit PSSC in the Interrupt Priority Register IP Bit Function Reserved for future use WCEN SSC Write Collision interrupt Enable WCEN 0 No interrup...

Page 101: ...erter to the SRI input allowing to check the transfer locally without a second SSC device TRIO SSC disable Tristate Mode of SSC inputs This bit should be used for test purposes only TRIO 0 The SSC ope...

Page 102: ...on chip peripherals Timer 0 Timer 1 Timer 2 USART and SSC and three of the interrupts may be triggered externally P1 1 T2EX P3 2 INT0 P3 3 INT1 A non maskable eighth interrupt is reserved for external...

Page 103: ...User s Manual 7 2 05 99 Interrupt System C513AO Figure 7 1 Interrupt Request Sources...

Page 104: ...t is not necessarily serviced Each interrupt requested by the corresponding flag can be enabled or disabled individually by the enable bits in the SFR IE This determines whether the requested interrup...

Page 105: ...rce is individually enabled or disabled by setting or clearing its enable bit ESSC SSC Interrupt Enable If ESSC 0 the interrupt of the Synchronous Serial Channel SSC is disabled ET2 Timer 2 Interrupt...

Page 106: ...pts are bits IE0 and lE1 in SFR TCON When an external interrupt is generated the flag that of this interrupt is cleared by hardware when the service routine is vectored to but only if the interrupt wa...

Page 107: ...f IT1 1 or released by external source if IT1 0 IT1 External interrupt 1 level edge trigger control flag If IT1 0 level triggered external Interrupt 1 is selected If IT1 1 negative edge triggered exte...

Page 108: ...eed to be cleared by software Special Function Register SCON Address 98H Reset Value 00H Bit Function TI Serial port Transmitter Interrupt flag TI is set by hardware at the end of the eighth bit time...

Page 109: ...ue 00H Bit Function TF2 Timer 2 Overflow Flag Must be cleared by software Set by a Timer 2 overflow TF2 will not be set when either RCLK 1 or TCLK 1 EXF2 Timer 2 External Flag Must be cleared by softw...

Page 110: ...cates that an attempt was made to write to the shift register STB while a data transfer was in progress and not fully completed This bit will be set at the trailing edge of the write signal during the...

Page 111: ...ity PT2 Timer 2 interrupt priority level If PT2 0 the Timer 2 interrupt has a low priority PS USART Serial Channel Interrupt Enable If PS 0 the Serial Channel interrupt has a low priority PT1 Timer 1...

Page 112: ...second priority structure determined by the polling sequence as shown in Table 7 2 A low priority interrupt can be interrupted by a high priority interrupt but not by another low priority interrupt A...

Page 113: ...toring to any service routine Condition 3 ensures that at least one more instruction will be executed before any interrupt is vectored to if the instruction in progress is RETI or any write access to...

Page 114: ...program but the interrupt control system would have behaved as if an interrupt were still in progress In this case no interrupt of the same or lower priority level would be acknowledged 7 4 External...

Page 115: ...ly listed If an interrupt of equal or higher priority is already in progress the additional wait time is determined by the nature of the other interrupt s service routine If the instruction in progres...

Page 116: ...period If the software fails to do this periodic refresh of the Watchdog Timer an internal hardware reset will be initiated The software can be designed such that the watchdog times out if the progra...

Page 117: ...lemented Reserved for future use OWDS Oscillator Watchdog Timer Status Flag Set by hardware when an oscillator watchdog reset occurs Can be set and cleared by software WDTS Watchdog Timer Status Flag...

Page 118: ...an internal reset will be initiated The reset cause either external reset or reset caused by the watchdog can be examined by software status flag WDTS in WDCON is set A refresh of the Watchdog Timer i...

Page 119: ...to 00H see Figure 8 1 The reload register WDTREL can be written at any time Therefore a periodic refresh of WDTREL can be included in the starting procedure of the Watchdog Timer Thus a wrong reload...

Page 120: ...sumes program execution Fast internal reset after power on The oscillator watchdog unit provides a clock supply for reset before the on chip oscillator has started The oscillator watchdog unit reset w...

Page 121: ...ure condition oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the input of the internal clock system to the output of the RC oscillator This mea...

Page 122: ...PCON1 is set wake up from power down mode enabled After start up of the watchdog circuitry in power down mode a power down mode wake up interrupt is generated instead of an internal reset 8 2 2 Fast...

Page 123: ...R PCON Furthermore register PCON contains two general purpose flags For example the flag bits GF0 and GF1 can be used to indicate that an interrupt occurred during normal operation or during an Idle M...

Page 124: ...Address 88H Reset Value 0XXXXXXXB Symbol Function Reserved for future use EWPD External Wake up From Power down Enable Bit Setting EWPD before entering Power down Mode enables external wake up from P...

Page 125: ...f all port pins both the pins controlled by their latches and those controlled by their secondary functions also depends on the status of the controller when entering Idle Mode Normally the port pins...

Page 126: ...ter the setting of this bit is achieved by byte handling instructions For example ORL PCON 00000001B Set IDLE bit The instruction which sets bit IDLE is the last instruction executed before going into...

Page 127: ...o machine cycles Slow down Mode is terminated by clearing bit SD Slow down Mode can be combined with Idle Mode by performing the following instruction ORL PCON 00010001B entering idle mode combined wi...

Page 128: ...of the instruction which initiated the Power down Mode ALE and PSEN are held at logic low level see Table 9 1 During Power down Mode operation VDD can be reduced to minimize power consumption It must...

Page 129: ...ower down Mode is entered Figure 9 1 shows the procedure which must be executed when Power down Mode is exited via the INT0 wake up capability of the C513AO If Power down Mode wake up capability has b...

Page 130: ...te To avoid any unintentional external interrupt request the user should ensure that P3 2 INT0 is set back to high level after a wake up request prior to completion of the wake up sequence MCT02597 AL...

Page 131: ...g Mode the C513AO 2E operates as a slave device similar to an EPROM stand alone memory device and must be controlled with address data information control lines and an external 11 5 V programming volt...

Page 132: ...amming Mode Figure 10 2 OTP Programming Mode Pin Configuration P DIP 40 top view C513AO 2E VDD 40 39 D0 38 D1 37 D2 36 D3 35 D4 34 D5 33 D6 32 D7 EA VPP 31 PROG 30 PSEN 29 28 27 A7 A6 26 A5 A13 A4 A12...

Page 133: ...E 28 A4 A12 27 26 25 24 23 22 21 20 19 18 A3 A11 A2 A10 A1 A9 A0 A8 V DD V SS XTAL1 XTAL2 N C N C N C 17 PALE 16 PRD 15 PSEL 14 PMSEL1 13 N C 12 PMSEL0 11 RESET 10 N C 9 N C 8 N C 7 40 41 42 43 44 1 2...

Page 134: ...2E 33 34 22 1 D4 D5 D6 D7 EA V PP N C PROG PSEN A6 A5 A13 A4 A12 A3 A11 A2 A10 A1 A9 A0 A8 VDD VSS XTAL1 XTAL2 N C N C N C PALE PRD PSEL PMSEL1 N C PMSEL0 RESET N C N C N C N C N C N C N C N C VSS VD...

Page 135: ...g edge of PALE When the logic level of PMSEL1 0 is changed PALE must be at low level PSEL 12 14 8 I Basic Programming Mode Select This input is used for the basic Programming Mode selection and must b...

Page 136: ...a low level must be applied to PROG EA VPP 31 35 29 Programming Voltage This pin must be at 11 5 V VPP voltage level during programming of an OTP memory byte or lock bit During an OTP memory read ope...

Page 137: ...c Programming Mode the OTP memory accesses are executed according to the selected Access Mode Access Modes include OTP memory byte program read signature byte read and program read lock byte operation...

Page 138: ...programming operations Note If Protection Level 1 to 3 has been programmed see Section 10 6 and Programming Mode has been left it is not possible to re enter Programming Mode 10 4 2 OTP Memory Access...

Page 139: ...emory programming cycle followed by an OTP memory read operation In this example A0 A13 of the read operation are identical to A8 A13 of the proceeding programming operation Figure 10 6 Programming Ve...

Page 140: ...TP memory bytes In this example OTP memory locations 3FDH to 400H are programmed Thereafter OTP memory locations 400H and 3FDH are read Figure 10 7 Typical OTP Memory Programming Verify Access Wavefor...

Page 141: ...ection Levels 1 to 3 has been programmed and Programming Mode has been left it is not possible to enter Programming Mode again Additionally in this case the lock bits can no longer be read Table 10 3...

Page 142: ...ad access To simplify the illustration the PROG pulse has been shortened In reality for Lock Bit programming a 100 s PROG low pulse must be applied Figure 10 8 Write Read Lock Bit Waveform MCT03365 PM...

Page 143: ...applied at the Port 1 address lines PALE must not be activated Figure 10 9 Read Version Byte s Waveform Version bytes are typically used by programming systems for adapting the programming firmware to...

Page 144: ...rol 4 4 Overlapping of data program memory 4 3 Program memory access 4 3 Program data memory timing 4 2 PSEN signal 4 3 Role of P0 and P2 4 1 F F0 3 9 F1 3 9 Fail save mechanisms 8 1 8 7 Fast power on...

Page 145: ...P 3 9 P0 3 6 3 8 P1 3 6 3 8 P2 3 6 3 8 P3 3 6 3 8 Parallel I O 6 1 6 14 PCON 3 6 3 7 3 8 6 33 PCON1 3 8 PCON14 3 7 PDE 3 8 Pin configuration 1 4 1 5 Pin definitions and functions 1 7 1 11 Ports 6 1 6...

Page 146: ...e mode 6 49 Registers 6 52 6 55 Slave mode timing 6 51 Write collision detection 6 48 SSCCON 6 52 SSCMOD 6 55 STB 3 9 6 55 SWDT 3 8 SYSCON 3 5 3 6 3 8 4 4 T T0 3 8 T1 3 8 T2 3 8 T2CON 3 7 3 9 7 8 T2EX...

Page 147: ...Reset operation 8 4 Starting of the WDT 8 3 Time out periods 8 3 WCEN 6 54 WCOL 7 9 WDCON 3 7 3 8 WDT 3 8 WDTPSEL 3 8 WDTREL 3 7 3 8 WDTS 3 8 WR 3 8 X XMAP 3 8 XRAM operation 3 3 Accessing twith DPTR...

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