AP29000
Connecting C166 and C500 Microcontroller to CAN
The Infineon CAN Devices C167CR, C515C and SAE 81C90/91
Application Note
32
V 1.0, 2004-02
The
Message Memory
contains the 16 message objects. The SAE 81C90/91 as well
owns a
Bit-Stream-Prozessor (BSP)
, which controls the complete CAN protocol,
handles the different CAN frames (Data Frame, Remote Frame), and performs the
frame check. The BSP reports errors to the
Error Management Logic
which returns
information about the error rate back to the BSP and to the
CPU Interface Logic
(CIL).
The CIL controls the accesses of the host CPU via the parallel or serial interface and
interprets the included instructions.
The task of the
Bit Timing Logic
is again the synchronization to the bit stream and the
bus timing. The
Transceiver Control Logic (TCL)
contains the output driver and the
input comparator. The
Transmit Check Unit
is a special feature of the SAE 81C90/91.
When transmitting a message, each bit is read back via the normal receive path and
compared with the bit just sent. If a mismatch occurs, the Transmit Check Error
Counter (TCEC) is incremented by one and the actual message is invalidated by an
Error Frame. In this way also the chip-internal conversion of the data stored in parallel
to the serial bit stream (which is not covered by the CAN protocol itself) is monitored. If
the TCEC reaches 4, the device enters the bus-off state.
4.3.3
The most important Control Registers of the SAE 81C90/91
Via the host CPU and the 8-bit control registers all functions of the SAE 81C90/91 are
controlled. The most important registers are described in the following section.
The register MOD contains the two bits IM and RES, which are necessary for the
initialization of the device, and some status bits. In the control register CTRL the
Monitor Mode of message object 1 and the Transmit Check Unit can be enabled. The
interrupt register INT shows occured interrupts which can be individually enabled /
disabled in the interrupt mask register IMSK. In the bit length registers BL1 and BL2
the bit timing segments TSEG1, TSEG2 and SJW are configured. The desired
baudrate is controlled via the baudrate prescaler register BRPR. Different physical
layers can be connected to the SAE 81C90/91 by programming the output control
register OC. The descriptor registers are filled with the 11 bits of the respective
identifier, the RTR bit (which distinguishes between Data- and Remote Frames), and
the data length code.
4.3.4
Initialization of the SAE 81C90/91 and Bus Access
Similar to the C167CR / C515C two special bits have to be set to be able to initialize
the device. These bits are IM and RES in the register MOD. Afterwards the registers
concerning the bit timing can be written and the message objects must be configured.
Resetting bits RES and IM ends the initialization phase and the controller can
participate in the CAN bus activities. Please also read section 5.5.1 for more
information about the initialization of this device.
