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AP29000

Connecting C166 and C500 Microcontroller to CAN

The Controller Area Network (CAN)

Application Note

19

V 1.0, 2004-02

The PROP_SEG (Propagation Segment) is used to compensate for signal delays
across the network. These delays are caused by signal propagation delay on the bus
line and through the electronic interface circuits of the bus nodes. PROP_SEG may be
1, 2, 3, ..., 8 or more Time Quanta long. For many CAN module implementations the
PROP_SEG and PHASE_SEG1 segments are combined for ease of programming.

The PHASE_SEG1 and PHASE_SEG2 segments are used to compensate for edge
phase errors. These segments may be lengthened or shortened by resynchronization.
PHASE_SEG1 may be 1, 2, 3, ..., 8 or more Time Quanta long. PHASE_SEG2 is the
maximum of PHASE_SEG1 and the information processing time, which is the time
segment starting with the sample point reserved for calculation of the subsequent bit
level and is less than or equal to two Time Quanta long. The sample point is the point
of time at which the bus level is read and interpreted as the value of that respective bit.
Its location is at the end of PHASE_SEG1.

The total number of Time Quanta in a bit time must be between 8 and 25.

As a result of resynchronization, PHASE_SEG1 may be lengthened or PHASE_SEG2
may be shortened. The amount of lengthening or shortening the phase buffer
segments has an upper limit given by the resynchronization jump width. The
resynchronization jump width may be between 1 and 4 Time Quanta, but it may not be
longer than PHASE_SEG1.

3.5

Error Detection and Error Handling

The CAN protocol provides sophisticated error detection mechanisms. The following
errors can be detected:

Cyclic Redundancy Check (CRC) Error

With the Cyclic Redundancy Check the transmitter calculates special check bits for the
bit sequence from the start of a frame until the end of the Data Field. This CRC
sequence is transmitted in the CRC Field. The receiving node also calculates the CRC
sequence using the same formula and performs a comparison to the received
sequence. If a mismatch is detected, a CRC error has occured and an Error Frame is
generated. The message is repeated.

Acknowledge Error

In the Acknowledge Field of a message the transmitter checks if the Acknowledge Slot
(which it has sent out as a recessive bit) contains a dominant bit. If not, no other node
has received the frame correctly, an Acknowledge Error has occured and the message
has to be repeated. No Error Frame is generated, though.

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Summary of Contents for C166 Series

Page 1: ...Application Note V 1 0 Feb 2004 CAN Connecting C166 and C500 Microcontroller to CAN Microcontrollers AP29000 N e v e r s t o p t h i n k i n g ...

Page 2: ...Content unchanged Controller Area Network CAN License of Robert Bosch GmbH CAN We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com ...

Page 3: ...MATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technol...

Page 4: ... 3 6 Different CAN Implementations 2 3 6 1 Standard CAN Extended CAN 2 3 6 2 Basic CAN Full CAN 2 4 The Infineon CAN Devices C167CR C515C and SAE 81C90 91 2 4 1 The Microcontroller Families C500 and C166 at a Glance 2 4 2 The CAN Module on the C167CR C515C 2 4 2 1 The Functional Blocks of the CAN Module 2 4 2 2 Control Registers of the CAN Controller 2 4 2 3 The Message Objects 2 4 2 4 Initializat...

Page 5: ...ling the CAN Module 2 6 4 1 The Initialization of the CAN Module on the C167CR C515C 2 6 4 2 The Transmission of a Data Frame with the CAN Module 2 6 4 3 The Transmission of a Remote Frame with the CAN Module 2 6 4 4 Evaluation of a received Message with the CAN Module 2 6 5 Ways of Handling the SAE 81C90 91 2 6 5 1 The Initialization of the SAE 81C90 91 2 6 5 2 The Transmission of a Data Frame Re...

Page 6: ...ollision Detection CTRL Control Register of the SAE 81C90 91 EML Error Management Logic IC Integrated Circuit IM Bit in the MOD Register of the SAE 81C90 91 INIT Bit in the Control Register of the CAN module INT Interrupt Register of the SAE 81C90 91 J1850 Protocol from Chrysler GM Ford MOD Status and Control Register of the SAE 81C90 91 NDA Non Destructive Arbitration NRZ Non Return to Zero PEC P...

Page 7: ...ollerfamilien C166 and C500 After the introduction Section 1 Section 2 introduces the reader to the Controller Area Network CAN Section 3 describes the Infineon CAN devices the 16 bit microcontroller C167CR the 8 bit microcontroller C515C and the Stand Alone Full CAN Controller SAE 81C90 91 Section 4 gives hardware examples for connection of Infineon microcontrollers to CAN Finally in Section 5 wa...

Page 8: ...rements due to its usage in a vehicle Data Rate Much of the data that is exchanged by the control systems or by sensors has to be processed in real time which requires very fast transmission Data items may differ in transmission priority e g Airbag data is likely to be high priority Air Conditioning data is likely to be low priority For very high priority data the latency period between the transm...

Page 9: ...obert Bosch GmbH in Germany These protocols mostly differ in transfer rate signal coding message format error detection and error handling The CAN protocol was defined by Bosch in the mid eighties For some time Infineon have also offered CAN devices such as the stand alone Full CAN controller SAE 81C90 91 and the C167CR and the C515C microcontrollers high end 16 bit or 8 bit microcontrollers respe...

Page 10: ...r There s no standard defined by CAN regarding the connector to be used The twisted wire pair is terminated by terminating resistors at each end of the bus line The maximum bus speed is 1 MBaud which can be achieved with a bus length of up to 40 m For bus lengths longer than 40 m the bus speed must be reduced a 1000 m bus can be realised with a 40 KBaud bus speed For a bus length above 1000 m spec...

Page 11: ...e Access collision of the messages is avoided by bitwise arbitration Collision Detection Non Destructive Arbitration together with the Wired AND mechanism dominant bits override recessive bits Each node sends the bits of its message identifier MSB first and monitors the bus level A node that sends a recessive identifier bit but reads back a dominant one loses bus arbitration and switches to receiv...

Page 12: ...data The Standard CAN Data Frame is shown in figure 1 In common with all other frames the frame begins with a Start Of Frame bit SOF dominant state for hard synchronization of all nodes Inter Frame Space 1 11 4 0 64 15 7 3 1 1 1 1 1 1 Standard Data Frame Bus Idle Intermission End of Frame ACK Delimiter ACK Slot CRC Delimiter Data Field Data Length Code Identifier Field Start of Frame Control Field...

Page 13: ...ta Field which is of the length defined by the DLC above 0 8 16 56 or 64 bits The Cyclic Redundancy Field CRC follows and is used to detect possible transmission errors The CRC Field consists of a 15 bit CRC sequence completed by the recessive CRC Delimiter bit The final field is the Acknowledge Field During the ACK Slot bit the transmitting node sends out a recessive bit Any node that has receive...

Page 14: ...r into 11bit most significant and 18 bit least significant sections This split ensures that the Identifier Extension bit IDE can remain at the same bit position in both standard and extended frames see below Inter Frame Space 1 11 4 0 64 15 7 3 1 1 1 1 1 Bus Idle Intermission End of Frame Data Field Data Length Code Start of Frame 18 Extended Data Frame ACK Delimiter ACK Slot CRC Delimiter CRC Seq...

Page 15: ...ntrol Field consisting of 6 bits The first 2 bits of this field are reserved and are at dominant state The remaining 4 bits of the Control Field are the Data Length Code DLC and specify the number of data bytes as for the Standard Data Frame The remaining portion of the frame Data Field CRC Field Acknowledge Field End Of Frame and Intermission is constructed in the same way as for a Standard Data ...

Page 16: ... The format of an Extended CAN Remote Frame is shown in figure 4 below Inter Frame Space 1 11 4 15 7 3 1 1 1 1 1 1 Bus Idle Intermission End of Frame ACK Delimiter ACK Slot CRC Delimiter Data Length Code Identifier Field Start of Frame Control Field CRC Sequence CRC Field reserved D IDE Bit D Acknowledge Field Standard Remote Frame RTR Bit R dominant Level recessive Level Arbitration Field ...

Page 17: ...llows the bus nodes to restart bus communications cleanly after an error There are however two forms of Error Flag fields The form of the Error Flag field depends on the error status of the node that detects the error see section 2 5 for details of error status Inter Frame Space 1 11 4 15 7 3 1 1 1 1 1 Bus Idle Intermission End of Frame Data Length Code Start of Frame 18 ACK Delimiter ACK Slot CRC...

Page 18: ...transmission of an Error Frame by an error passive node will not affect any other node on the network If the bus master node generates an error passive flag then this may cause other nodes to generate error frames due to the resulting bit stuffing violation After transmission of an Error Frame an error passive node must wait for 6 consecutive recessive bits on the bus before attempting to rejoin b...

Page 19: ...nstructed from an integer multiple of Time Quanta The Time Quantum is the smallest discrete timing resolution used by a CAN node A bit time and therefore by definition also the bit rate is selected by programming the Bit Timing Logic BTL to select the width of the Time Quanta and the number of Time Quanta in the various segments The nominal bit time with its segments according to CAN Spec ISO11898...

Page 20: ...f Time Quanta in a bit time must be between 8 and 25 As a result of resynchronization PHASE_SEG1 may be lengthened or PHASE_SEG2 may be shortened The amount of lengthening or shortening the phase buffer segments has an upper limit given by the resynchronization jump width The resynchronization jump width may be between 1 and 4 Time Quanta but it may not be longer than PHASE_SEG1 3 5 Error Detectio...

Page 21: ...epeated as soon as possible Furthermore each CAN node is in one of the three error states error active error passive oder bus off according to the value of the internal error counters The error active state is the usual state where the bus node can transmit messages and active Error Frames made of dominant bits without any restrictions In the error passive state messages and passive Error Frames m...

Page 22: ...gement has to be done by software i e by the host CPU Mostly the CAN chip also only provides one transmit buffer and one or two receive buffers So the host CPU load is quite high using Basic CAN modules therefore these devices should only be used at low baudrates and low bus loads with only a few different messages The advantages of Basic CAN are the small chip size leading to low costs of these d...

Page 23: ... instructions in just one machine cycle of 80 ns 25 MHz CPU clock The freely programmable interrupt system has response times of typically 400 ns and can handle a large number of independent internal and external interrupt sources at 16 priority levels The family members SAB 80C166 C167 C165 and C163 are equipped with a well balanced mix of modular autonomous peripherals like a 10 bit ADC with up ...

Page 24: ...s of the CAN module are organized as 16 bit registers located on word addresses However all registers may be accessed bytewise in order to select special actions without affecting other mechanisms These registers reside in a special CAN address area of 256 bytes which is mapped into segment 0 and uses addresses EF00h through EFFFh In the C515C the CAN module is connected to the internal bus Again ...

Page 25: ...d the bus line The BSP also controls the Error Management Logic EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages which have been corrupted by noise or other external error condit...

Page 26: ...and to define the position of the Sample Point in the bit time The programming of the BTL depends on the baudrate and on external physical delay times The Intelligent Memory CAM RAM Array provides storage for up to 15 message objects of maximum 8 data bytes length Each of these objects has a unique identifier and its own set of control and status bits After the initial configuration the Intelligen...

Page 27: ...t 1 General Registers CAN Address Area General Registers F700H F710H Message Object 2 F720H Message Object 3 F730H Message Object 4 F740H Message Object 5 F750H Message Object 6 F760H Message Object 7 F770H Message Object 8 F780H Message Object 9 F790H Message Object 10 F7A0H Message Object 11 F7B0H Message Object 12 F7C0H Message Object 13 F7D0H Message Object 14 F7E0H Message Object 15 F7F0H Sta...

Page 28: ...t position of the message s identifier is not relevant during the acceptance filtering In this way a message object accepts not only one specific message but all messages only differing in the previously masked bits The last message object MO 15 is used for the Basic CAN feature EF00H EF02H EF04H EF06H EF08H EF0CH EF00H EF10H EF20H EF30H EF40H EF50H EF60H EF70H EF80H EF90H EFA0H EFB0H EFC0H EFD0H ...

Page 29: ...with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a Remote Frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a Remote Frame can be sent to request that the appropriate object be ...

Page 30: ...ontrol High Upper Arbitration Low 0 1 2 3 4 5 6 Message Object Reserved Upper Arbitration High Lower Arbitration Low Lower Arbitration High Message Control Low Message Configuration Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 7 8 9 10 1 12 13 14 15 Start Address Message Control Arbitration Message Config 0 2 4 6 6 8 10 12 14 Object Start Address ...

Page 31: ...d SAE 81C91 P LCC 28 package without I O Ports can be operated with up to 20 MHz They support the CAN spezification V2 0A B passive i e the controllers can handle messages with the 11 bit standard identifier Frames with the 29 bit extended identifier are not stored but tolerated Via a flexible programmable interface the connection to different implementations of the physical layer ISO OSI layer 1 ...

Page 32: ...igure 12 Figure 12 Block Diagram of the SAE 81C90 91 I O Ports only available for SAE 81C90 Time Stamp Transmit Check CPU Interface Logic Message Memory CAM Array RAM Parallel Interface PI CS RD WR ALE INT MS AD 0 AD 7 Bit Stream Processor Error Management Logic I O Port P0 I O Port P1 Clock Generator Oscillator X1 X2 CLKOUT RES output driver logic input logic TX0 TX1 RX0 RX1 Bit Timing Logic Seri...

Page 33: ...state 4 3 3 The most important Control Registers of the SAE 81C90 91 Via the host CPU and the 8 bit control registers all functions of the SAE 81C90 91 are controlled The most important registers are described in the following section The register MOD contains the two bits IM and RES which are necessary for the initialization of the device and some status bits In the control register CTRL the Moni...

Page 34: ...C and SAE 81C90 91 Application Note 33 V 1 0 2004 02 The SAE 81C90 91 contains no implementation of the physical layer which again requires a CAN transceiver Further information about the SAE 81C90 91 Stand Alone Full CAN Controller can be found in section 5 or in the corresponding Data Sheet ...

Page 35: ... this example the CAN bus is a shielded twisted wire pair with termination resistors at both ends of the bus lines If the transceiver has an input pin for slope control or stand by it can be driven via a port pin of the C167CR pin P4 7 in this case Notes If the CAN module is used port 4 may not be programmed to output all eight segment address lines A maximum of four segment address lines is possi...

Page 36: ...ation Note 35 V 1 0 2004 02 Figure 13 Connection of the C167CR to CAN Figure 14 shows the connection between the C515C and the CAN bus This time the CAN module is connected to the CAN transceiver via the port pins RXDC and TXDC of port 4 For the control of a slope control or stand by pin portpin P4 5 was chosen in this example ...

Page 37: ...th I O ports is shown Both controllers are connected via the multiplexed 8 bit bus address data lines AD0 to AD7 signals WR RD ALE This parallel connection is selected by applying a low logic level to pin MS a high level would activate the serial interface With the aid of the remaining address lines AD8 to AD17 the chip select signal for the CAN controller active low can be generated via decoding ...

Page 38: ...MHz clock information Like the C167CR C515C the SAE 81C90 contains no implementation of the physical layer and therefore a transceiver must be used This driver module is connectd to the SAE 81C90 via pins TX0 Transmitter Output 0 set as a push pull output by software here and RX0 Comparator Input 0 Digital input Neither the second transmit pin TX1 nor the analog input RX1 is required here RX1 is a...

Page 39: ... the SAE 81C91 The 8 bit microcontrollers C511 C513 are new low cost members of the C500 family The SAE 81C90 91 is an obvious choice for using one of these devices in a Controller Area Network just as it is for the SAB 80C166 In contrast to the the example shown in figure 16 however the SAE 81C91 P LCC 28 without I O ports was selected in the circuit shown in figure 4 3 1 It is connected to the C...

Page 40: ...on of the controllers is done via the line SCLK CLK Data from pin DI are always transferred into the internal shift register with the rising edge of the clock The level applied to the timing pin TIM of the CAN controller decides whether data is output at the DO pin with the rising edge TIM 0 or with the falling edge TIM 1 see figure 4 3 1 of the CLK signal Pin P1 7 of the C511 C513 controls the sl...

Page 41: ...e respective register Via pointer these names have been connected with the respective address in three include files Therefore in the software hints not address EF04h of the C167CR is accessed but directly the register BTR the Bit Timing Register Those registers which appear more than once e g in each message object are given the name adder _M1 _M2 etc for message object 1 2 etc Another possibilit...

Page 42: ...har 0xf707 define UGML0 unsigned char 0xf708 define UGML1 unsigned char 0xf709 define LGML0 unsigned char 0xf70a define LGML1 unsigned char 0xf70b define UMLM0 unsigned char 0xf70c define UMLM1 unsigned char 0xf70d define LMLM0 unsigned char 0xf70e define LMLM1 unsigned char 0xf70f define MCR0_M1 unsigned char 0xf710 define MCR1_M1 unsigned char 0xf711 define UAR0_M1 unsigned char 0xf712 define UA...

Page 43: ...TRSR2 unsigned char far 0x 09 define IMSK unsigned char far 0x 0a define MOD unsigned char far 0x 10 define INT unsigned char far 0x 11 define CTRL unsigned char far 0x 12 define DR0H unsigned char far 0x 40 define DR0L unsigned char far 0x 41 define DR1H unsigned char far 0x 42 define DR1L unsigned char far 0x 43 define BYTE0MSG0 unsigned char far 0x 80 define BYTE1MSG0 unsigned char far 0x 81 de...

Page 44: ...ly In the following section a way to determine these parameters for a special controller frequency e g 20 MHz and a certain CAN baudrate e g 125 kbit s shall be presented The calculations are based on the following rough structure of one bit time figure 17 Figure 17 Rough Structure of one Bit Cell in the CAN Module of the C167CR C515C and in the SAE 81C90 91 The following equations apply to figure...

Page 45: ...CLOCK 1 CLP 1 fCPU The following equation applies to SAE 81C90 91 tCAN_CLOCK 2 tOSC 2 fOSC Equations 2 3 and 4 inserted into 1 results in tBIT 1 t q TSEG1 1 tq TSEG2 1 tq which is equal to tBIT 3 tq TSEG1 TSEG2 tq This equation solved to TSEG1 TSEG2 results in TSEG1 TSEG2 tBIT 3 tq tq Inserting 5 results in TSEG1 TSEG2 tBIT BRP 1 tCAN_CLOCK 3 The following applies to TSEG1 TSEG2 1 TSEG1 TSEG2 22 a...

Page 46: ...ount General rules for TSEG1 and TSEG2 depending on BRP Table 3 if BRP 0 if BRP 1 TSEG1 2 TSEG1 1 TSEG2 1 TSEG2 0 As a general rule the sampling of the bit should take place at about 60 70 of the total bit time Nevertheless for each system the delays of bus drivers transmitter receiver circuits and the bus lines have to be taken into account when configuring the sample point Examples can be found ...

Page 47: ...d So a SJW of 1 should be enough With other baudrates and clock frequencies the calculation can be done in the same way On request three EXCEL tools CP_167CR XLS CP_81C90 XLS CP_C515C XLS are available which calculate proposals for the different parameters from the used frequency and baudrate 6 4 Ways of Handling the CAN Module 6 4 1 The Initialization of the CAN Module on the C167CR C515C The ini...

Page 48: ...1 BTR0 0 1 0 0 0 0 0 1 TSEG2 TSEG1 SJW BRP If Standard CAN is used then the Global Mask Short has to be initialized according to the identifier bits to be used for acceptance filtering application specific Shall all bits of the 11 bit identifier be evaluated then all respective bits of the Global Mask Short are set to 1 C167CR GMS 0xE0FF Global Mask Short Adr EF06h 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 ...

Page 49: ... Bits 4 3 2 1 0 2 1 0 9 8 7 6 5 0 12 C515C UGML0 0xFF Upper Gl Mask Long Low Adr F708h UGML1 0xFF Upper Gl Mask Long High Adr F709h 1 1 1 1 1 1 1 1 UGML1 UGML0 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 Id Bits 2 2 2 2 2 2 2 2 0 9 8 7 6 5 4 3 13 28 8 7 6 5 4 3 2 1 LGML0 0xFF Lower Gl Mask Long Low Adr F70Ah LGML1 0xF8 Lower Gl Mask Long High Adr 7F0Bh 1 1 1 1 1 0 0 0 LGML1 LGML0 1 1 1 1 1 1 1 1 Id Bits 1 1 1...

Page 50: ... 0 2 1 1 1 1 1 1 1 Ident Bits 2 2 2 2 2 2 2 2 0 9 8 7 6 5 4 3 13 28 8 7 6 5 4 3 2 1 LMLM0 0x00 Lower Mask of Last Mess Low F70Eh LMLM0 0x00 Lower Mask of Last Mess High F70Fh 0 0 0 0 0 0 0 0 LMLM1 LMLM0 0 0 0 0 0 0 0 0 Ident Bits 1 1 1 4 3 2 1 0 0 12 2 1 0 9 8 7 6 5 Please also see section 5 6 for the use of the Basic CAN feature Then the message objects are configured For this reason Message Conf...

Page 51: ...bject will generate If a Data Frame with a matching identifier is received If a Remote Frame with a matching identifier is received DIR Bit 0 Receive Object receives Data Frames transmits Remote Frames a Remote Frame The corresponding Data Frame is stored in this MO on reception the Data Frame is stored the Remote Frame is NOT answered DIR Bit 1 Transmit Object transmits Data Frames receives Remot...

Page 52: ...ure identifier example for Standard CAN 11 bit identifier C167CR UAR_Mn 0xE068 Upper Arbitr Reg n Adr EFn2h 1 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Identifier Bits 0 9 8 7 6 5 4 3 8 7 6 5 4 3 2 1 13 28 LAR_Mn 0x0000 Lower Arbitr Reg n Adr EFn4h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 res 1 1 1 9 8 7 6 5 Identifier Bits 2 1 0 0 12 C515C UAR0_Mn 0x68 Upper Arbitr Reg n Low ...

Page 53: ...incoming Remote Frame CPUUPD has to be kept set until the data bytes have been filled with real data Receive objects do not have a CPUUPD field This field is called MSGLST in these objects and is set by the CAN controller if a new message comes in before the previously received message has been read out Example for a transmit object which shall not generate interrupts C167CR MCR_Mn 0x5995 Configur...

Page 54: ...7_Mn 0x00 Finally all message objects that will not be used have to be declared as not valid C167CR MCR_Mn 0x5555 reset all functions incl MSGVAL C515C MCR0_Mn 0x55 reset all functions incl MSGVAL MCR1_Mn 0x55 Clearing bits INIT and CCE ends the initialization Setting the bits IE Interrupt Enable SIE Status Change Interrupt Enable and EIE Error Interrupt Enable at the same time enables all interru...

Page 55: ...e reset C167CR CSR 0xFFF7 Reset TXOK C515C SR 0xF7 Reset TXOK Then CPUUPD CPU Update and NEWDAT New Data of the transmit object s corresponding Message Control Register should be set to show that the CPU now wants to work on the data bytes of this transmit object C167CR MCR_Mn 0xFAFF Set CPUUPD and NEWDAT C515C MCR1_Mn 0xFA Set CPUUPD and NEWDAT RMTPND unchanged TXRQ unchanged CPUUPD set NEWDAT se...

Page 56: ...ets TXRQ and RMTPND sets bit TXOK in the Status Register and generates a status change interrupt if enabled in the Control Register IE 1 SIE 1 If TXIE is set in the respective Message Control Register a transmit interrupt is generated if enabled in the Control Register IE 1 6 4 3 The Transmission of a Remote Frame with the CAN Module Make sure that you have configured a valid message object as rec...

Page 57: ...be reset C167CR MCR_Mn 0xFDFF reset NEWDAT C515C MCR1_Mn 0xFD reset NEWDAT RMTPND unchanged TXRQ unchanged MSGLST unchanged NEWDAT reset MSGVAL unchanged TXIE unchanged RXIE unchanged INTPND unchanged 6 4 4 Evaluation of a received Message with the CAN Module If the C167CR or the C515C receive a message with a matching identifier this can either be a data or a Remote Frame If a Remote Frame is rec...

Page 58: ... ECAN of the Special Function Register IEN2 In the interrupt service routine the reason for the interrupt status change interrupt or interrupt of one of the message objects can be read from the contents of the Interrupt Register the so called INTID INTerrupt IDentifier If bit SIE in the Control Register has been set and the CAN controller updated not necessarily changed the Status Register which i...

Page 59: ... access also reads the status partition of this register If you want to read the control partition without the clearing of the Status Change INTID use byte access to the low byte of the Control Status Register Reading the Status Register in the C515C has the same effect of clearing the Status Change INTID 3 The Interrupt with the lowest INTID has the highest priority If an interrupt with a higher ...

Page 60: ...ddr 00h BL2 0x41 load BL2 Digital Input Addr 01h 0 1 0 0 1 0 0 1 BL1 BL2 0 1 0 0 0 0 0 1 S TSEG2 TSEG1 I D S SJW A P I M M O L In the Interrupt Mask Register IMSK bit ERI is set to globally enable interrupts to the host controller generated by incoming messages Other interrupts on completed transmissions on reception of a Remote Frame on entering the bus off state etc can be enabled as well if des...

Page 61: ...91 In the descriptor bytes the identifier of the message objects and the length of the Data Field is configured The values have to be chosen according to the message objects in other CAN nodes the SAE 81C90 91 shall communicate with With the RTR bit the SAE 81C90 91 distinguishes between message objects handling only Data Frames RTR 0 or handling only Remote Frames RTR 1 Please mind the following ...

Page 62: ...tain identifier certain DLC RTR 1 This corresponds to a transmit object in the CAN module of the C167CR C515C without the possibility of sending its own Data Frames though load descriptor bytes of MO n Example Identifier 1001 0110 000 RTR 0 DLC 8 DRnH 0x96 load descriptor high byte object n DRnL 0x08 load descriptor low byte object n Byte H 1 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 Byte L IDENTIFIER RTR DLC...

Page 63: ...n be loaded with the desired message DLC 4 here BYTE3MSGn 0x33 load data byte 3 obj n with 33h BYTE2MSGn 0x22 load data byte 2 obj n with 22h BYTE1MSGn 0x11 load data byte 1 obj n with 11h BYTE0MSGn 0x00 load data byte 0 obj n with 00h Please take care that writing must end with data byte 0 as mentioned in the previous section about the initialization of the device The message is transmitted by se...

Page 64: ...When now the corresponding Data Frame arrives it will be stored in this message object as long as there s no other message object with RTR 0 the same identifier and a higher message object priority You have to make sure though that the reprogramming of the RTR bit is done before the corresponding Data Frame is transmitted Be also aware of the fact that the requested Data Frame is not necessarily t...

Page 65: ...ponding bit in the Receive Ready Register RRR1 5 here RRR1 0xDF clear bit RRR1 5 INT RI will be cleared by the SAE 81C90 91 if all receive interrupts have been serviced and no more receive ready bits are set 6 6 How to use the Basic CAN Features of the CAN Module and the SAE 81C90 91 6 6 1 The Basic CAN Feature of the CAN Module The Basic CAN Feature of the CAN module works with message object 15 ...

Page 66: ...hould be set to 0 Example for standard frames Global Mask Short 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ANDed with Upper Mask of Last Message 0 0 0 x x x x x 0 0 0 0 0 0 0 0 bits to be masked to be don t care d d d d d d d d d d d d Upper Arbitration Register of MO 15 x x x x x x x x x x x x x x x x Identifiers stored d d d x x x x x d d d d d d d d Identifiers ddddddddddd 00000000000 11111111111 Scenario...

Page 67: ...and NEWDAT if a Data Frame was received INTPND NEWDAT and RMTPND if a Remote Frame was received This will release the momentarily accessed buffer 5 The CPU now has to check INTID in the interrupt register again If INTID is no longer 02 but has been updated by the CAN controller to 00 or an other value both buffers of MO 15 are released If INTID is still 02 then the other buffer of MO15 is still al...

Page 68: ... RIM0 in the RIMR1 register both are set an interrupt is generated If a Remote Frame arrives 1 that does not match with one of the other MOs 1 15 the Remote Frame is stored in MO 0 The descriptor bytes are updated with the identifier and the data length code DLC of the Remote Frame 0 The RTR bit is set to 1 The data bytes of MO 0 are not overwritten by the Remote Frame because the Remote Frame con...

Page 69: ...h t t p w w w i n f i n e o n c o m Published by Infineon Technologies AG ...

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