TC1796
System Units (Vol. 1 of 2)
Introduction
User’s Manual
1-11
V2.0, 2007-07
Intro, V2.0
– 16 Kbyte Instruction Cache (ICACHE)
– 16 Kbyte Boot ROM (BROM)
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Data memory
– 64 Kbyte Data Memory (SRAM)
– 16 Kbyte data memory (SBRAM) for standby operation during power-down
– 56 Kbyte Local Data RAM (LDRAM)
– 8 Kbyte Dual-port RAM (DPRAM)
– 128 Kbyte on-chip Data Flash (DFLASH)
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PCP
– 32 Kbyte PCP Code Memory (CMEM)
– 16 Kbyte PCP Data Memory (PRAM)
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On-chip SRAMs with parity error detection
Interrupt System
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Total of 181 Service Request Nodes (SRNs)
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Flexible interrupt-prioritizing scheme with 255 interrupt priority levels
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Fast interrupt response
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Service requests are serviced by CPU or PCP
Peripheral Control Processor (PCP)
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Data move between any two memory or I/O locations
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Data move until predefined limit reached supported
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Read-Modify-Write capabilities
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Full computation capabilities including basic MUL/DIV
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Read/move data and accumulate it to previously read data
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Read two data values and perform arithmetic or logical operation and store result
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Bit-handling capabilities (testing, setting, clearing)
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Flow-control instructions (conditional/unconditional jumps, breakpoint)
DMA Controller
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16 independent DMA channels
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Programmable priority of the DMA sub-blocks on the bus interfaces
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Buffer capability for move actions on the buses (minimum of 1 move per bus is
buffered).
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Individually programmable operation modes for each DMA channel
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Full 32-bit addressing capability of each DMA channel
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Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
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Micro Link bus interface support
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One register set for each DMA channel
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Flexible interrupt generation
