IKA AMM36, User Manual

Page: 34 / 56

AMM36 • SSI, BiSS, & RS-485
6.3 Control Data CD
Main control data is described in this section. Please refer to the official BiSS
documents for complete CD structure: “BiSS C Protocol Description” in the BiSS
homepage.
Register address
It sets the number of the register you need either to read or to write. It is 7-bit
long.
RW
RW
= “01”: when you need to write in the register.
RW
= “10”: when you need to read in the register.
It is 2-bit long.
DATA
When you need to write in a register ( RW = “01”), it allows to enter the value to
be written in the register (transmitted from the Master to the Slave).
When you need to read in a register (
RW
= “10”), it shows the value read in the
register (transmitted from the Slave to the Master).
It is 8-bit long.
Data bit structure:
bit 7 … … 0
msb … … lsb
CRC
Correct transmission control (inverted output). Cyclic Redundancy Check is an
error checking which is the result of a “Redundancy Check” calculation
performed on the message contents. This is intended to check whether
transmission has been performed properly. It is 4-bit long.
Polynomial: X
4 +X 1 +1 (binary: 10011)
Logic circuit:
MAN AMM36 SSI_BiSS_RS485 E 1.0.odt 6 - BiSS C-mode interface 34 of 56
1st
stage
2nd
stage
3rd
stage
4th
stage
X 0
X
1
X
2
X
3
Input Data (starts from MSB)