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©Copyright 2000-2007 SD Card Association  

SDIO Simplified Specification Version 2.00 

 27 

6.4 Suspend/Resume 

 
Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to 
the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards 
can implement the 

optional

 concept of suspend/resume. If a card supports suspend/resume, the host may 

temporarily halt a data transfer operation to one function or memory (suspend) in order to free the bus for a 
higher priority transfer to a different function or memory. Once this higher-priority transfer is complete, the 
original transfer is re-started where it left off (resume). Support of suspend/resume is optional on a per-card 
basis. If suspend/resume is implemented, it shall be supported by the memory (if any) of a Combo card and all 
I/O functions 

except

 0 (the CIA). Note that the host can suspend multiple transactions and resume them in any 

order desired. I/O function 0 does 

not

 support suspend/resume. Suspend/Resume is described in more detail in 

section 9. Any card that supports Suspend/Resume shall also support Read Wait and Direct Commands (SRW 
and SDC = 1) Note that Suspend/Resume is defined only for the SD 1 and 4-bit modes. It does not apply to SPI 
transfers. 
 

6.5 Read 

Wait 

 
Host devices built to the SD Physical Specification shall control the SDCLK to stop the read data block output 
from a card executing a multiple read command whenever the host cannot accept more data. During the time 
that the host has stopped the SDCLK, a CMD52 cannot be issued. This limitation causes a problem in that a 
host device built to the SD Physical Specification cannot perform the I/O command during a multiple read cycle. 
 
In order to eliminate this limitation, the SDIO Specification adds the Read Wait control to enable the host to issue 
CMD52 during a multiple read cycle. Read Wait uses the DAT[2] line to allow the host to signal the card to 
temporarily halt the sending of read data by a card. This feature is optional for an SDIO or combo card. However, 
if an SDIO or combo supports Read Wait, all functions and any memory shall support Read Wait. Read Wait is 
described in more detail in section 10. Any card that supports Suspend/Resume shall also support Read Wait. 
Note that Read Wait is defined only for the SD 1 and 4-bit modes. It does not apply to SPI transfers. 
 

6.6 

CMD52 During Data Transfer 

 
A card may accept CMD52 during data transfer if it supports Direct Commands (see SDC, Table 6-3). For both SD 
and SPI modes

, if an error occurs during data transfer the SDIO card shall accept CMD52 to allow I/O abort and 

reset regardless of this bit value of the value of SDC. 
 

6.7 

SDIO Fixed Internal Map 

 
The SDIO card has a fixed internal register space and a function unique area. The fixed area contains 
information about the card and certain mandatory and optional registers in fixed locations. The fixed locations 
allow any host to obtain information about the card and perform simple operations such as enable in a common 
manner. The function unique area is a per-function area, which is defined either by the Application 
Specifications for Standard SDIO functions or by the vendor for non-standard functions. Figure 6-1 shows the 
internal map of an SDIO card with multiple functions. 

Summary of Contents for SDIO Card

Page 1: ...SD Specifications Part E1 SDIO Simplified Specification Version 2 00 February 8 2007 Technical Committee SD Card Association ...

Page 2: ...0 1 Added method to change bus speed Normal Speed up to 25MHz and High Speed up to 50 MHz 2 Operational Voltage Requirement is extended to 2 7 3 6V 3 Combine sections 12 Physical Properties and 13 Mechanical Extensions and add miniSDIO to the new section 13 Physical Properties 4 Add Embedded SDIO ATA Standard Function Interface Code 5 Reference of Physical Ver2 00 supports SDHC combo card 6 Some t...

Page 3: ...plementation of the Simplified Specification may require a license from the SD Card Association or other third parties Disclaimers The information contained in the Simplified Specification is presented only as a standard specification for SD Cards and SD Host Ancillary products and is provided AS IS without any representations or warranties of any kind No responsibility is assumed by the SD Card A...

Page 4: ...ith a space dividing each group of four digits as in 1000 0101 0010b All other numbers are decimal Key Words May Indicates flexibility of choice with no implied recommendation or requirement Shall Indicates a mandatory requirement Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification Should Indicates a strong recommendati...

Page 5: ...s SDIO only or SD Memory only after Combo Initialization 12 3 4 3 Acceptable Commands after Initialization 12 3 4 4 Recommendations for RCA after Reset 12 3 4 5 Enabling CRC in SPI Combo Card 14 4 Differences with SD Memory Specification 15 4 1 SDIO Command List 15 4 2 Unsupported SD Memory Commands 15 4 3 Modified R6 Response 16 4 4 Reset for SDIO 16 4 5 Bus Width 16 4 6 Card Detect Resistor 17 4...

Page 6: ...errupt Period Definition 40 8 1 4 Interrupt Period at the Data Block Gap in 4 bit SD Mode Optional 40 8 1 5 Inhibited Interrupts Removed Section 40 8 1 6 End of Interrupt Cycles 40 8 1 7 Terminated Data Transfer Interrupt Cycle 41 8 1 8 Interrupt Clear Timing 41 9 SDIO Suspend Resume Operation 42 10 SDIO Read Wait Operation 43 11 Power Control 44 11 1 Power Control Overview 44 11 2 Power Control s...

Page 7: ... SDIO Specific Extensions 53 16 7 1 CISTPL_FUNCID Function Identification Tuple 53 16 7 2 CISTPL_FUNCE Function Extension Tuple 54 16 7 3 CISTPL_FUNCE Tuple for Function 0 common 54 16 7 4 CISTPL_FUNCE Tuple for Function 1 7 55 16 7 5 CISTPL_SDIO_STD Function is a Standard SDIO Function 58 16 7 6 CISTPL_SDIO_EXT Tuple Reserved for SDIO Cards 58 Appendix A 59 A 1 SD and SPI Command List 59 Appendix...

Page 8: ...ions 36 Table 6 5 Card Information Structure CIS and reserved area of CIA 37 Table 11 1 Reference Tuples by Master Power Control and Power Select 45 Table 16 1 Basic Tuple Format 51 Table 16 2 Tuples Supported by SDIO Cards 52 Table 16 3 CISTPL_MANFID Manufacturer Identification Tuple 53 Table 16 4 CISTPL_FUNCID Tuple 53 Table 16 5 CISTPL_FUNCE Tuple General Structure 54 Table 16 6 TPLFID_FUNCTION...

Page 9: ...SDIO aware host 9 Figure 3 4 IO_SEND_OP_COND Command CMD5 10 Figure 3 5 Response R4 in SD mode 11 Figure 3 6 Response R4 in SPI mode 11 Figure 3 7 Modified R1 Response 11 Figure 3 8 Re Initialization Flow for I O Controller 13 Figure 3 9 Re Initialization Flow for Memory controller 13 Figure 5 1 IO_RW_DIRECT Command 21 Figure 5 2 R5 IO_RW_DIRECT Response SD modes 22 Figure 5 3 IO_RW_DIRECT Respons...

Page 10: ...l change to memory driver software Extended physical form factor available for specialized applications Plug and play PnP support Multi function support including multiple I O and combined I O and memory Up to 7 I O functions plus one memory supported on one card Allows card to interrupt host Operational Voltage range 2 7 3 6V Operational Voltage is used for Initialization Application Specificatio...

Page 11: ... pins and signaling protocols are identical to the SD Physical Specification 2 2 2 1 bit SD Data Transfer Mode Card Mandatory Support This mode is identical to the 1 data bit narrow mode defined for SD Memory in section 3 6 1 of the SD Physical Specification In this mode data is transferred on the DAT 0 pin only In this mode pin 8 which is undefined for memory is used as the interrupt pin All othe...

Page 12: ... Simplified Specification Version 2 00 3 2 4 Signal Pins Figure 2 1 Signal connection to two 4 bit SDIO cards The rest of this chapter is not included in the Simplified Specification SD Host CLK SD I O Card CMD DAT 3 0 SD I O Card DAT 3 0 CMD CLK ...

Page 13: ...ry commands An I O only card shall not respond to the ACMD41 and thus appear initially as an MMC card See appendix B 1 for information on the MMC specification The I O only card shall also not respond to the CMD1 used to initialize the MMC cards and appear as a non responsive card The host then gives up and disables this card Thus the non aware host receives no response from an I O only card and f...

Page 14: ... of the card see 6 8 This is done by issuing a read command starting with the byte at address 0x00 of I O function 0 The CIA contains the Card Common Control Registers CCCR and the Function Basic Registers FBR Also included in the CIA are pointers to the card s common Card Information Structure CIS and each individual function s CIS The CIS structure is defined in section 16 The CIS includes infor...

Page 15: ...O 0 MEM 0 No Response Re init Memory MEM 0 IO Initialized Get IO OCR Set New Voltage if needed CMD8 is required to support High Capacity Memory CMD5 Arg 0 Check Response CMD5 Arg WV Check Response A Power On NF 0 or OCR invalid NF 0 OCR valid IORDY 0 1sec Timeout Unusable card Inactive State IORDY 1 CMD8 Check Response F8 1 F8 0 Unusable card CMD0 Pin1 High Test IO Flag CMD52 IO Reset No Response ...

Page 16: ...1 Arg HCS WV Check Response A OCR valid MRDY 0 1sec Timeout Unusable card Inactive State MRDY 1 Test MEM Flag Skip memory initialize or MEM 1 Execute memory initialize MEM 0 B MEM 1 CMD2 CMD3 Test Flags Not SD Card Unusable card Inactive State CMD15 RCA 0 OCR invalid Test IO Flag IO 1 IO 0 IO 0 MEM 1 IO 1 MEM 1 IO 1 MEM 0 No Response No Response High Capacity Support Host HCS 1 Memory Initialized ...

Page 17: ... 1sec Timeout IORDY 1 CMD8 Check Response F8 1 F8 0 Unusable card CMD0 CS Low Test IO Flag CMD52 IO Reset Illegal Command Error Response Good Response Re init IO Test MP D IO 1 MP 1 MP 0 IO 0 IO 0 MEM 0 Illegal Command IO Initialized Get IO OCR Skip IO Initialize or IO 1 Execute IO Initialize IO 0 Set New Voltage if needed Re init Memory MEM 0 CMD8 is required to support High Capacity Memory ...

Page 18: ...y Initialized Skip memory initialize or MEM 1 Execute memory initialize MEM 0 Get memory OCR Standard Capacity Memory Only Card High Capacity Memory Only Card Standard Capacity Combo Card High Capacity Combo Card Test CCS Test CCS CCS 0 CCS 1 CCS 0 CCS 1 Variables NF Number of I O Functions CMD5 Response MP Memory Present Flag CMD5 Response IORDY I O Power up Status C bit in the CMD5 response MRDY...

Page 19: ...es transfer from host to card Command Index Identifies the CMD5 command with a value of 000101b Stuff Bits Not used shall be set to 0 I O OCR Operation Conditions Register The supported minimum and maximum values for VDD The layout of the OCR is shown in Table 3 1 See section 4 10 1 for additional information CRC7 7 bits of CRC data E nd bit End bit always 1 I O OCR bit position VDD Voltage Window...

Page 20: ...1 if Card is ready to operate after initialization I O OCR Operation Conditions Register The supported minimum and maximum values for VDD The layout of the OCR is shown in Table 3 1 See section 4 10 1 for additional information Memory Present Set to 1 if the card also contains SD memory Set to 0 if the card is I O only Number of I O Functions Indicates the total number of I O functions supported b...

Page 21: ...elect de select is accomplished using the hardware CS line rather than the RCA 3 4 1 Re initialize both I O and Memory When the host re initializes both I O and Memory controllers it is strongly recommended that the host either execute a power reset power off then on or issues a reset commands to both controllers prior to any other operation If the host chooses to use the reset commands it shall i...

Page 22: ...er has transitioned to the cmd state Figure 3 9 Re Initialization Flow for Memory controller Combo Init After CMD7 with the correct RCA Issue CMD52 Reset I O Re initialize I O CMD5 Issue CMD3 Issue CMD7 with the correct RCA and Data Transfer Card RCA Select Deselect Mem State I O State RCA1 Select tran cmd Sel Desel xxxx RCA2 Deselect Deselect xxxx RCA2 Desel Sel tran tran tran tran cmd idle stby ...

Page 23: ...any commands except for CMD0 ACMD41 with RCA 0x0000 CMD2 CMD3 or CMD7 to the Combo Card until the memory controller has transitioned to the tran state 3 4 5 Enabling CRC in SPI Combo Card When receiving CMD59 Combo cards shall synchronize CRC enable in both SDIO and memory portions of the card If a host enables CRC using CMD59 and subsequently re initializes either the I O or memory controller the...

Page 24: ...card or the I O portion of a combo card is not reset with CMD0 CMD12 CMD52 write to I O abort In order to abort the block transfer of data SD memory use CMD12 In order to abort an I O transaction use CMD52 to write to the abort register in the CCCR bits 2 0 of register 6 See 4 8 for details CMD16 CMD52 write to I O Block Length CMD16 sets the block length for SD memory In order to set the block le...

Page 25: ...O only cards Host should ignore these bits Note Please refer to sections 7 3 4 of the SD Physical Specification for explanation of the entries in the Type and Clear Condition columns Table 4 3 SDIO R6 Status Bits 4 4 Reset for SDIO In order to reset all functions within an SDIO card or the SDIO portion of a combo card a method different than that used for SD memory is defined The reset command CMD...

Page 26: ...ure to enable disable this resistor is different between SD memory and SDIO SD memory uses ACMD42 to control this resistor while SDIO uses writes to the CCCR using CMD52 In the case of a combo card both control locations exist and shall be managed by the host For a combo card the resistor is enabled only when both the memory and the I O control registers have the resistor enabled That is after a p...

Page 27: ...le the host is issuing the abort The rest of this section is not included in the Simplified Specification 4 9 2 Write Abort The host may issue an I O abort by writing to the CCCR at any time between data blocks during I O extended write operation In this case the final block transfer including the CRC response from the card shall have been completed This requires that the end bit of the I O abort ...

Page 28: ...d with an Invalid Command error response and a card in SD mode shall not respond 4 10 4 RCA Register There shall only be one RCA register per SD card The RCA value shall apply to the card as a whole All functions and any memory share the same card address 4 10 5 DSR Register SDIO only cards do not support the DSR register In the case of combo cards support is optional as defined in the SD Physical...

Page 29: ...d state Note 2 B 21 CARD_ECC_FAILED N A 0 Not used with SDIO operation C 20 CC_ERROR N A 0 Not used with SDIO operation C 19 ERROR E R 0 no error 1 error A general or an unknown error occurred during the operation C 18 UNDERRUN N A 0 Not used with SDIO operation C 17 OVERRUN N A 0 Not used with SDIO operation C 16 CID CSD_OVERWRITE N A 0 Not used with SDIO operation C 15 WP_ERASE_SKIP N A 0 Not us...

Page 30: ...ead data from the SDIO card at the address specified by the Function Number and the Register Address to the host The data byte is returned in the response R5 If this bit is set to 1 the command shall write the bytes in the Write Data field to the I O location addressed by the Function Number and the Register Address If the RAW flag is 0 then the data in the register that was written shall be read ...

Page 31: ...tion Direction 0 indicates transfer card to host Response Command Index Identifies the IO_RW_DIRECT command with a value of 110100b Stuff Bits Not used shall be set to 0 Response Flags 8 Bits of flag data indicating the status of the SDIO card Table 5 1 shows the format of these flag bits Read or Write Data For an I O write R W 1 with the RAW Flag set RAW 1 this field shall contain the value read ...

Page 32: ... error 1 error The command s argument was out of the allowed range for this card C Table 5 1 Flag data for IO_RW_DIRECT SD Response 5 2 2 R5 IO_RW_DIRECT Response SPI mode The SDIO card s response to CMD52 in the SPI mode is shown in Figure 5 3 If the operation was a read command the data being read is returned as an 8 bit value In addition 8 bits of status information is returned in a SPI R1 resp...

Page 33: ... common I O area CIA Block Mode Optional this bit if set to 1 indicates that the read or write operation shall be performed on a block basis rather than the normal byte basis If this bit is set the Byte Block count value shall contain the number of blocks to be read written The block size for functions 1 7 is set by writing the block size to the I O block size register in the FBR See Table 6 3 and...

Page 34: ...see Table 6 1 and Table 6 2 Table 5 3 shows the relationship between the value in the command and the actual number of bytes transferred CRC7 7 bits of CRC data E nd bit End bit always 1 The response from the SDIO card to CMD53 shall be R5 the same as CMD52 as defined in 5 2 For CMD53 the 8 bit data field shall be stuff bits and shall be read as 0x00 Also the ERROR response bit shall be type E R X...

Page 35: ...out value relates to the time for the requested data to be transferred to from the host on the DAT x lines and not the timing between the command and the response This wait time is signaled to the host by the card using busy for a write or delaying the start bit for a read operation The host can use 1 second as the timeout value for a non responding location If a functions needs to support an acce...

Page 36: ...the SDCLK a CMD52 cannot be issued This limitation causes a problem in that a host device built to the SD Physical Specification cannot perform the I O command during a multiple read cycle In order to eliminate this limitation the SDIO Specification adds the Read Wait control to enable the host to issue CMD52 during a multiple read cycle Read Wait uses the DAT 2 line to allow the host to signal th...

Page 37: ...e and interrupts on a per card master and per function basis The bits in the CCCR are mixed Read Write and read only If any of the possible 7 functions are not provided on an SDIO card the bits corresponding to unused functions shall all be read only and read as 0 All reserved for future use bits RFU shall be read only and return a value of 0 All writeable bits are set to 0 after power up or reset...

Page 38: ...F Ready Flags RF7 RF6 RF5 RF4 RF3 RF2 RF1 RFM 0x10 0x11 FN0 Block Size I O block size for Function 0 0x 12 Power Control Reserved for Future Use RFU EMPC SMPC 0x 13 High Speed RFU RFU RFU RFU RFU RFU EHS SHS 0x14 0xEF RFU Reserved for Future Use RFU 0xF0 0xFF Reserved for Vendors Area Reserved for Vendor Unique Registers Table 6 1 Card Common Control Registers CCCR Field Type Description CCCRx R O...

Page 39: ...o 1 then this function s interrupt shall be sent to the host if the master Interrupt Enable bit 0 is also set to 1 IENM R W Interrupt Enable Master If this bit is cleared to 0 no interrupts from this card shall be sent to the host If this bit is set to 1 then any function s interrupt shall be sent to the host INTx R O Interrupt Pending for function x If this bit is cleared to 0 this indicates that...

Page 40: ...le data transfer to a different address on the card is underway CMD52 is described in 5 1 In any case SD or SPI mode if an error occurs during data transfer the SDIO card shall accept CMD52 to allow I O abort and reset regardless of this bit value If the card supports suspend resume then it shall also support this bit SMB R O Card Supports Multi Block This flag bit reports the SDIO card s ability ...

Page 41: ...d Resume protocol If the card does not support Suspend Resume this bit shall be read as 0 Any access to the CIA may not be suspended so in this case BS shall always be set to 1 irrespective of the host setting BR to 1 BR R W Bus Release Request Status This bit is used to request that the addressed function selected by FSx or by the function number in CMD53 or Memory commands using DAT line release...

Page 42: ...tinue data transfer the card shall return DF 0 to abort the transfer EXx R O Execution Flag bits 7 0 These bits are used by the host to determine the current execution status of all functions 1 7 and memory 0 The bit is set to 1 for each function or memory that is currently executing a command The EXx bits tell the host that a function or memory is currently executing a command so no additional co...

Page 43: ...t SHS R O Support High Speed This flag bit reports the card s ability to operate in High Speed mode SHS 0 The card does not support High Speed mode SHS 1 The card supports High Speed mode The host enables High Speed mode via the EHS bit See section 12 for details on switching between default and High Speed mode EHS R W Enable High Speed EHS 0 default The card operates in default timing mode with a...

Page 44: ... interface code R O The SDIO Standard Function code identifies those I O functions which implement the recommended standard interface as defined in a separate Application Specification A complete and current list of assigned standard codes shall be maintained and published in any addendums to this specification The codes assigned to those standard interfaces at the time this specification was publ...

Page 45: ... pointer only the lower 17 bits are used to the start of the Card Information Structure CIS that is associated with each function The CIS is defined in section 6 11 A CIS is mandatory for each function on an SDIO card This pointer is stored in little endian format LSB first This register points to the End of Chain tuple if the function is not supported on the card Address pointer to Function CSA R...

Page 46: ...n the card Multiple Function SDIO Cards shall use a combination of a CIS common to all functions on the card and a separate function specific CIS specific to each function on the card The common CIS describes features that are common to all functions on the card Each function specific CIS describes features specific to a particular function on the SDIO Card Functions are numbered sequentially begi...

Page 47: ...Command State Dat Bus Free BS 0 Transfer State Dat Bus Active BS 1 Inactive State CMD3 CMD52 Reset CMD7 with correct RCA CMD7 with incorrect RCA CMD53 to valid function Function Resume Execution complete Function Suspend CMD52 Abort CMD52 Reset CMD15 or OCR mismatch CMD7 with correct RCA CMD53 to invalid function Commands accepted in CMD CMD7 CMD52 CMD53 CMD15 Commands accepted in TRN CMD52 Comman...

Page 48: ...0n0E where n is the function number 0x1 to 0x7 Once the start address is written data can be read or written by accessing register 0x00n0F the CSA data window register If more than 1 byte needs to be read or written an extended I O command byte or block can be performed with an OP code of 0 fixed address The address pointer shall be automatically incremented with each access to the window register...

Page 49: ... host is responsible for clearing the interrupt If the SDIO card is operating in the SPI mode the interrupt from the card may not be asserted if the card is not selected CS 0 The exception to this requirement occurs only if the card is both capable of interrupting when not selected the SCSI bit in the CCCR 1 and has that feature turned on the ECSI bit 1 In this case the card may assert the interru...

Page 50: ...condition may allow an interrupt that has already been handled to re interrupt the host if the timing of the interrupt clear is not controlled To prevent this condition Any SDIO card that implements interrupts shall follow some required timing with respect to removing the interrupt from the DAT 1 line after the write to the function unique area that clears the interrupt The clearing of the interru...

Page 51: ...the lower priority or slower transaction to suspend 3 The host checks for the transaction suspension to complete 4 The host begins the higher priority transaction 5 The host waits for the completion of the higher priority transaction 6 The host restores the suspended transaction If the current transaction can accept suspend and the card receives a suspend command during Read Wait it shall accept t...

Page 52: ...ds to any function within the SDIO card To determine if a card supports the Read Wait protocol the host shall test SRW capability bit in the Card Capability byte of the CCCR see Table 6 1 The timing for Read Wait is based on the Interrupt Period that is defined in section 8 1 If a card does not support the Read Wait protocol the only means a host has to stall not abort data in the middle of a read...

Page 53: ...ity of trying to use a standard power card in a host that does not have enough power to meet the card s requirement In this case the card will fail to operate Cards supporting Power Selection will enable the widest range of host support Power Selection is supported on a per function basis and available to the host in the FBR 11 2 Power Control support for SDIO Cards 11 2 1 Master Power Control SDI...

Page 54: ...ined in 3 1 3 5V or 2 7 3 6V range When a new voltage range is added in future specification another six tuples will be added Table 11 1 shows which tuples a host shall refer to depending on the host version and the settings of EMPC and EPS bits Host EMPC EPS Reference TPLs Comments Ver 1 0 Don t care Don t care TPLFE_OP_MIN_PWR TPLFE_OP_AVG_PWR TPFLE_OP_MAX_PWR Ver 1 1 0 Don t care TPLFE_SP_AVG_P...

Page 55: ...e of two power modes for the function A host that can supply enough power to the card does not need to use Power Selection If SMPC is set to 1 and SPS is set to 1 the host can utilize Power Selection by setting EMPC to 1 If EPS is set to 0 default mode of the card Higher Current Mode is selected If EPS is set to 1 Lower Current Mode is selected For example a wireless function may offer a power mod...

Page 56: ...lly the card switches the card bus speed mode If two bus speed switch commands are executed in turn to the same bus speed mode only the first successful command is effective to switch bus speed mode The host needs to check success of executing bus speed switch command and then the host can switch the host bus speed mode to the same one Success of switching bus speed mode is determined by checking ...

Page 57: ... Addendum Version 2 00 Part 1 Physical Layer Specification Version 2 00 for that portion of the card that is not extended When a miniSDIO card is inserted into a miniSD to SD memory card adaptor and plugged into an SDIO host slot it shall appear to the host as an SDIO card The rest of this section is not included in the Simplified Specification 14 SDIO Power 14 1 SDIO Card Initialization Voltages ...

Page 58: ...Simplified Specification Version 2 00 49 itself as drawing more power that the host is willing to supply thus lower power cards may have a competitive advantage in the market The rest of this chapter is not included in the Simplified Specification ...

Page 59: ... Copyright 2000 2007 SD Card Association SDIO Simplified Specification Version 2 00 50 15 Inrush Current Limiting This chapter is not included in the Simplified Specification ...

Page 60: ... For all other tuples byte 1 of each tuple contains a link to the next tuple in the chain If the link field is 0 then the tuple body is empty If the link field contains 0xFF then this tuple is the last tuple in its chain There are two ways of marking the end of a tuple chain for SDIO cards a tuple code of 0xFF or a tuple link of 0xFF The use of an FFH link value is allowed in SDIO cards but it is ...

Page 61: ...onal data fields in tuples should be ignored using the link field For example if a scan program is expecting 0x15 bytes of data and the TPL_LINK field indicates a size of 0x19 bytes the scan program should ignore and skip over the last 4 bytes of data 16 5 SDIO Card Metaformat Unlike the PCMCIA card the SDIO card has multiple CIS areas There is a common CIS for the entire card and a CIS assigned t...

Page 62: ...rer code In this case the most significant eight bits shall be zero 0 For example if a JEDEC manufacturer code is 89H their SDIO Card manufacturer code is 0x0089 If a SDIO card manufacturer does not currently have a TPLMID_MANF assigned one can be obtained at little or no cost from the PCMCIA The TPLMID_CARD field is reserved for the use of the SDIO Card s manufacturer It is anticipated that the f...

Page 63: ...Byte 7 6 5 4 3 2 1 0 0x00 TPL_CODE CISTPL_FUNCE 0x22 0x01 TPL_LINK Link to next tuple 0x04 0x02 TPLFE_TYPE Type of extended data 0x00 0x03 0x04 TPLFE_FN0_BLK_SIZE 0x05 TPLFE_MAX_TRAN_SPEED Table 16 6 TPLFID_FUNCTION Tuple for Function 0 common The fields in this tuple have the following definition Field Description TPLFE_FN0_BLK_SIZE This is both the maximum block size and byte count that function...

Page 64: ...G_PWR_3 3V 0x2A 0x2B TPLFE_LP_MAX_PWR_3 3V Table 16 8 TPLFID_FUNCTION Tuple for Function 1 7 The fields in this tuple have the following definition Field Description TPLFE_FUNCTION_INFO Bit significant information about the Function The bits are defined in Table 16 10 TPLFE_STD_IO_REV This 8 bit value contains the version level of the Application Specification for Standard SDIO Functions that this...

Page 65: ...ater TPLFE_SB_AVG_PWR This is the average current in mA required by this function when in the standby condition If this function does not support standby this value shall be 0x00 The method to place this function in the standby state and the capabilities it has while in standby are vendor defined This value is valid for all voltages supported by this function Note that this value is valid only for...

Page 66: ...escriptions for Functions 1 7 Bit 7 6 5 4 3 2 1 0 Name RFU RFU RFU RFU RFU RFU RFU FN_WUS Table 16 10 TPLFE_FUNCTION_INFO Definition The FN_WUS Wake Up Support bit signals the function s support of wake up when the function is placed into a low power state and the SDCLK is stopped The intent is to allow a SDIO card to be placed into a low power condition and still signal the host of a wake up even...

Page 67: ...s tuple supplies additional information The available codes can be found in the I O device interface code entry of the FBR see 6 10 TPLSDIO_STD_TYPE This 8 bit value identifies the format and type of data contained within the body of this tuple If this value is 0x00 then only 1 standard data structure has been defined for this Standard SDIO Function If this value is non zero then this byte identif...

Page 68: ...ot supported by SDIO CMD12 STOP_TRANSMISSION Mandatory CMD13 SEND_STATUS Mandatory Card Status includes only SDMEM information CMD15 GO_INACTIVE_STATE Mandatory Mandatory CMD16 SET_BLOCKLEN Mandatory CMD17 READ_SINGLE_BLOCK Mandatory CMD18 READ_MULTIPLE_BLOCK Mandatory CMD24 WRITE_BLOCK Mandatory CMD25 WRITE_MULTIPLE_BLOCK Mandatory CMD27 PROGRAM_CSD Mandatory CSD not supported by SDIO CMD28 SET_W...

Page 69: ...andatory CMD24 WRITE_BLOCK Mandatory CMD25 WRITE_MULTIPLE_BLOCK Mandatory CMD27 PROGRAM_CSD Mandatory CSD not supported by SDIO CMD28 SET_WRITE_PROT Optional CMD29 CLR_WRITE_PROT Optional CMD30 SEND_WRITE_PROT Optional CMD32 ERASE_WR_BLK_START Mandatory CMD33 ERASE_WR_BLK_END Mandatory CMD38 ERASE Mandatory CMD42 LOCK_UNLOCK Optional CMD52 IO_RW_DIRECT Mandatory CMD53 IO_RW_EXTENDED Mandatory Bloc...

Page 70: ...w SD Specifications after Version 2 00 1 SD Specifications Part 1 PHYSICAL LAYER SPECIFICATION Version 2 00 May 9 2006 2 SD Specifications Part 1 miniSD Card Addendum Version 2 00 January 30 2007 3 SD Specifications Part 2 FILE SYSTEM SPECIFICATION Version 2 00 May 9 2006 4 ISO IEC9293 1994 Information technology Volume and file structure of disk cartridges for information interchange 5 PC CARD ST...

Page 71: ...ECC Error Correction Code Embedded SDIO I O or combo devices that are embedded in a host device that utilize the SDIO electrical and command interface but are not intended to be removed EMI Electro Magnetic Interference ESC External Signal Contacts ESD Electro Static Discharge FAT File Allocation Table FBR Function Basic Registers FIFO First In First Out buffer Flash A type of multiple time progra...

Page 72: ...ata transfer RFU Reserved for Future Use Normally Read Only and set to 0 ROM Read Only Memory RWC Read Wait Control SCR SD Configuration Register SDA SD Association SDCLK SD clock signal SDIO SD Input Output SDIO aware A host designed to support the signals and protocol of SDIO devices SPI Serial Peripheral Interface Standard Power SDIO A SDIO device that operates with 200 mA or less of current at...

Page 73: ... Copyright 2000 2007 SD Card Association SDIO Simplified Specification Version 2 00 64 Appendix D Informative Appendix D is not included in the Simplified Specification The Last Page ...

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