QUICK START GUIDE
EPC90132
EPC – POWER CONVERSION TECHNOLOGY LEADER |
| ©2021 |
| 2
DESCRIPTION
The EPC90132 is a half bridge development board with onboard gate
drives, featuring the 40 V rated EPC2055 GaN field effect transistor (FET).
The purpose of this development board is to simplify the evaluation
process of the EPC2055 by including all the critical components on a
single board that can be easily connected into the majority of existing
converter topologies.
The EPC90132 development board measures 2” x 2” and contains two
EPC2055 GaN FET in a half bridge configuration and one EPC2038 GaN
FET used to augment the bootstrap supply. The EPC90132 features the uPI
Semiconductor uP1966A gate driver. The board also contains all critical
components and the layout supports optimal switching performance.
There are also various probe points to facilitate simple waveform
measurement and efficiency calculation. A block diagram of the circuit
is given in figure 1.
please refer to their datasheets
available from EPC at
. The datasheet should be read in
conjunction with this quick start guide.
Table 1: Performance Summary (T
A
= 25°C) EPC90132
Symbol
Parameter
Conditions
Min Nominal Max Units
V
DD
Gate Drive Regulator
Supply Range
7.5
12
V
V
IN
Bus Input Voltage
Range
(1)
32
V
I
OUT
Switch Node Output
Current
(2)
25
A
V
PWM
PWM Logic Input
Voltage Threshold
(3)
Input ‘High’
3.5
5.5
V
Input ‘Low’
0
1.5
V
PWM ‘High’ State Input
Pulse Width
V
PWM
rise and
fall time < 10ns
50
ns
PWM ‘Low’ State Input
Pulse Width
(4)
V
PWM
rise and
fall time < 10ns
200
ns
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing
must be kept under 40 V for EPC2055.
(2) Maximum current depends on die temperature – actual maximum current is affected by
switching frequency, bus voltage and thermal cooling.
(3) When using the on board logic buffers,
refer to the uP1966A datasheet when bypassing
the logic buffers
.
(4) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
EPC90132 development board
Back view
Front view
Figure 1: Block diagram of EPC90132 development board default configuration
Lev
el shif
t
V
DD
V
IN
Switch node
Q
1
Q
2
C
Bypass
PWM
GND
C
out
Gate drive
regulator
Gate driver
DC Output
PGND
Logic and
dead-time
adjust
L
1
