4. Internal Switching Fabric > Packet Queuing
95
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
In some systems, it is necessary to guarantee maximum throughput for a burst (continuous sequence)
of packets at the same priority. In a congested system, it is possible that only one buffer is available for
these packets. This can restrict throughput on the egress port, since while one packet in the burst is
being transmitted and is awaiting acknowledgment, another packet in the burst cannot be accepted or
transmitted. Watermarks can be used to guarantee that two buffers are available for these packets.
When two buffers are available, while one packet is transmitted and awaits acknowledgement another
packet can be accepted. This leads to an increase in throughput for packets in the burst.
If a packet cannot be admitted by the ingress buffer, the packet is dropped and a RETRY is sent to the
link partner. The RETRY control symbol begin transmission within 12 SYS_CLK cycles of the
reception of the first 4 bytes of the packet. This allows the link partner to select another packet for
transmission that has a higher probability of being accepted by the link partner.
The Tsi578 provides performance registers that system software can use to determine the extent of
input congestion on the switch (refer to
“IDT-Specific Performance Registers” on page 331
).
shows which priorities of packets can be accepted given the number of free buffers.
4.4.3
Input Arbitration
When packets are placed in a single input queue, head-of-line (HOL) blocking can result. HOL occurs
when the packet at the head of a queue is blocked, and the packets must remain in the same order. This
means that no packet in the queue can be sent across the ISF, even if all the packets, save the first, have
an uncongested path to their respective destinations.
The ISF manages HOL blocking by reordering packets in a manner compliant with the
RapidIO
Interconnect Specification (Revision 1.3)
. This technique may allow another packet to proceed if the
packet at the head of a queue is blocked, depending on the arbitration mode selected. In other words the
packets are reordered in the queue, but this reordering never violates the RapidIO packet ordering
rules.
Three modes are supported and can be configured with the IN_ARB_MODE field in the
:
•
First come, first served (default)
•
Strict Priority #1
•
Strict Priority #2
Each time the internal switching fabric reorders a packet within its queues
1
, the Tsi578 increments a
16-bit counter field (CTR) in the
“RapidIO Port x Reordering Counter Register” on page 360
affected port. This value can be monitored as an indication of the level of switching congestion. The
register also contains a threshold. When the counter is incremented and its new value equals the
threshold, the Tsi578 raises the maskable INB_RDR interrupt. This interrupt is masked with the
“RapidIO Port x Interrupt Status Register” on page 326
The number of times a packet is reordered is configurable (see
).
1. Counting the number of times a packet is reordered within a queue is different from counting the number of times packets are actually
sent out of order. The switching fabric might reorder the queue several times before finding one packet to send.
