IDT Tsi578, User Manual

Page: 71 / 527

3. Serial RapidIO Electrical Interface > Clocking 71
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
The data rate of all the ports in Tsi578 at power-up is determined by the setting of the
SP_IO_SPEED[1:0] pins (see
“Signal Descriptions” ). There is only one pair of SP_IO_SPEED pins for
the entire device, which means all RapidIO ports default to the same speed at power-up. After reset, the
individual port speeds can be configured through registers (IO_SPEED in
“SRIO MAC x Digital
Loopback and Clock Selection Register” on page 377 ) or through the I
2
C configuration EEPROM.
The RapidIO Interconnect Specification (Revision 1.3) requires the receive and transmit signals must
operate at the same baud rate. This means a port must transmit at the same clock rate that it receives
/-100 ppm.
3.4.1 Changing the Clock Speed
The following procedure changes the signaling rate of a port:
1. Set PWDN_X4 in the “SRIO MAC x Digital Loopback and Clock Selection Register” on page 377
to 1
2. Select the new clock speed using IO_SPEED in the SMACx_DLOOP_CLK_SEL register
3. Set PWDN_X4 in the SMACx_DLOOP_CLK_SEL to 0
For more information about powering down ports and special requirements for powering down port 0,
see
“Port Power Down” on page 72 .
3.4.2 Changing the Clock Speed Through I
2
C
The Tsi578 can be configured to power up with ports at different link speeds by setting the “SRIO
MAC x Digital Loopback and Clock Selection Register” on page 377 by an external I
2
C master access
or by an EEPROM boot load.
The most effective way to configure the port link speed through the I
2
C register load is to leave the port
powered down at boot time through the SP{n}_PWRDN configuration pin (see “Signal Descriptions” )
and have entries in the I
2
C EEPROM to load the appropriate contents of the
SMACn_DLOOP_CLK_SEL to power up the port and set the correct port speed.
When ports in the same MAC are both operating in 1x mode, both ports operate at the same
rate.
The settings of SP_IO_SPEED[1:0] pins and the reference clock used have a strict
relationship. Entering an illegal setting causes unpredictable behavior of the device.
Care must be taken writing this register by an I
2
C master because the port is initialized before
the I
2
C load is completed and therefore must follow the same rules as outlined in “Changing
the Clock Speed” on page 71 .
Initializing the port speed using an I
2
C EEPROM boot load must also follow the rules
outlined in “Changing the Clock Speed” on page 71 because the port is loaded with the
power-up option selection on reset release and, although the port is prevented from
initializing during the EEPROM boot load, the PLL is running.