3. Serial RapidIO Electrical Interface > Port Aggregation: 1x and 4x Modes
69
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
The PWRDNx4 and PWRDNx1 bits must both be asserted prior to changing the state of the
MAC_MODE bit. Therefore, changing the MAC operation from x4 to two x1 or from two x1 to x4
operation requires that the ports both be powered down using the PWRDNx4 and PWRDNx1 bits, and
then powered back up with the new setting of the MAC_MODE bit.
The port width in use can be different from the pin-selected width; the pin indicates what the port was
set to operate at, while the registers show what it is actually operating at. An even port with the
capability to function in either 1x or 4x mode port can be downgraded to a 1x mode port when faults on
lanes prevent operation in 4x mode. Additionally, the port width can be overridden through register
programming and changed into operating at a different port mode. Refer to
for status and control fields for port width and
for downgraded port configuration.
3.3.1
1x + 1x Configuration
When the 4x mode-capable port in a Tsi578 MAC is configured to operate in 1x mode, the
odd-numbered port in a MAC can also be used in 1x mode. In this configuration, the even-numbered
port always uses SerDes lane A and the odd-numbered port always uses SerDes lane B.
The two ports that share the same MAC also share the same transmit clock, which means the two ports
must have the same bit rate. To select the bit rate, write the IO_SPEED field (see
Digital Loopback and Clock Selection Register” on page 377
), as described in
.
The initial clock rate is selected by the global power-up option for all ports.
3.3.2
4x Configuration
When the even-numbered port in a Tsi578 MAC is configured to operate in 4x mode (for example port
0), the odd-numbered port in a MAC (for example port 1) cannot be used and the register values for the
odd-numbered port should be ignored. To save power, the odd-numbered port can be powered down
(see
).
The even-numbered port configured for 4x mode follows the link-width negotiation rules outlined in
the
RapidIO Interconnect Specification (Revision 1.3)
. Depending on the configuration or capabilities
of the link partner, or on the quality of the connection, it is possible that a port configured for 4x mode
actually operates in 1x mode on either SerDes lane A or C. Under this scenario, the degraded port can
not be configured to an 1x + 1x mode.
A port’s operation is not affected if the SPx_MODESEL signal values are changed after they
have been sampled at reset release.
The unusable, odd-numbered port is still a part of the Tsi578’s memory map. However,
system software must be aware that the port is not usable and that its per-port registers should
not be accessed. If the port is accessed the Tsi578’s behavior is undefined. Refer to
for more details on register behavior under power down conditions.
