IDT Tsi578, User Manual

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10. Clocks, Resets and Power-up Options > Clocks 207
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
10.1.2 SerDes Clocks
All SerDes in Tsi578 use the same external reference clock (S_CLK_p/n). Depending on the pin or
register setup, the SerDes generates the appropriate clocks to serialize/deserialize the data as well as the
clocks for the internal logic. On the Receive side, each lane of the SerDes recovers their own clocks.
These clocks can be powered down by register controls (
“SRIO MAC x SerDes Configuration Global”
on page 372 ).
10.1.3 Reference clocks
The two reference clocks are described in Table 26 .
Ti
p
For information on configuring the clock rate of RapidIO ports, refer to “Clocking” on
page 70 .
Table 26: Tsi578 Input Reference Clocks
Clock Input Pin Type Frequency
a
a. For more electrical characteristics of the clocks, please refer to the
Tsi578
Hardware Manual .
Clock Domains
S_CLK_p/n Differential 156.25MHz
b
b. For more information about operation at alternative S_CLK frequencies, refer to “Line Rate Support” on page 489 .
Serial Transmit Domain (Maximum 156.25 MHz)
Internal Switching Fabric (ISF) Domain
P_CLK
c
c. For more information on programming additional frequencies for the P_CLK, refer to “P_CLK Programming” on page 493 .
Single-ended 100 MHz Internal Register Domain
I
2
C Domain