IDT TSI384, User Manual

Page: 119 / 281

10. Reset, Clocking, and Initialization 119
Tsi384 User Manual
May 5, 2014
Integrated Device Technology
www.idt.com
The clock speed of the PCI/X bus is determined by the settings of PCI_PCIXCAP, PCI_SEL100, and
PCI_M66EN, as described in
Table 31 . Since this is clock slave mode, this is only used for determining
if Tsi384 clock tree insertion compensation should be used. The PLL used in the clock insertion
compensation block is specified for performance above 33 MHz. The main issue with a PCI clock at or
below 33 MHz is that it may stop being clocked. This makes the PLL design problematic, and thus,
clock insertion compensation is not used.
Table 32 summarizes the slave behavior of the Tsi384. If the decoded clock speed is above 33 MHz
then clock tree compensation is used.
10.3 Initialization
When the Tsi384 comes out of reset (level 0, 1, or 2), its clock speed and capabilities are determined
according to
Table 29 when in clock master mode, and Table 31 when in clock slave mode. This allows
the Tsi384 to set its programmable PLL divided ratios when it is clock master, or muxing in/out the
clock compensation when it is clock slave.
Table 31: Slave Mode and Clock Rate
Mode and Bus Rate PCI_PCIXCAP PCI_SEL100 PCI_M66EN
Clock Insertion
Compensation
PCI 25 MHz GND 1 0 No
PCI 33 MHz GND 0 0 No
PCI 50 MHz GND 1 1 Yes
PCI 66 MHz GND 0 1 Yes
PCI-X 50 MHz 10K to ground 1 1 Yes
PCI-X 66 MHz 10K to ground 0 1 Yes
PCI-X 100 MHz High 1 1 Yes
PCI-X 133 MHz High 0 1 Yes
Table 32: Slave Mode Clock Insertion Compensation
Mode
PWRUP_EXT_
CLK_SEL Bus Speed
Slave without Tsi384 Clock tree compensation 0

33 MHz
Slave with Tsi384 Clock tree compensation 0 >33 MHz