6
Tsi340 Evaluation Board User Manual
80E3000_MA002_02
Integrated Device Technology
www.idt.com
2.2
Clocking
Tsi340 is a synchronous device, where the secondary clock outputs are synchronous to the primary
clock input.
Figure 2
shows the PCI clocking connection.
Figure 2: Clock Signals
2.2.1
Domains
Primary and secondary clocking domains are described in the following sections.
2.2.1.1
Primary PCI Clock Domain
The primary clock is sourced from a PCI host. It must be synchronous with the primary PCI bus
(according to the
PCI Specification (Revision 2.3)
)
The PCI host sets the clock frequency based on its M66EN signal level. However, the Tsi340
evaluation board has the option of forcing the PCI host's M66EN signal low with a DIP switch setting
on S1. Refer to
“DIP Switch Package/ Individual Switch Position” on page 14
for more information.
2.2.1.2
Secondary PCI Clock Domain
Tsi340 has four secondary clock outputs, which provide PCI_CLKin for four on-board PCI connectors.
The secondary clock outputs are derived from the primary PCI clock input.
2.2.2
M66EN Signal
The M66EN signal from the primary side PCI finger connector is directly routed to four on-board PCI
connectors. A DIP switch is attached to M66EN that is used to force M66EN to ground so that the
33 MHz PCI clock can be set. Refer to
“DIP Switch Package/ Individual Switch Position” on page 14
for more information.
P_CLK
S_CLK_OUT0
S_CLK_OUT1
S_CLK_OUT2
S_CLK_OUT3
Tsi340
DIP
Switch
Secondary PCI
32bit 33/66MHz
Primary PCI
32bit 33/66MHz
PCI_M66EN