5. Configuration Registers
78
Tsi310 User Manual
80B6020_MA001_05
5.4.7
Cache Line Size Register
This register specifies the cache line size in 32-bit DWord units (not used when the interface is
in PCI-X mode).
Address Offset
x‘0C’
Access
Read/Write
Reset Value
x‘00’
Restrictions
Only one bit can be set at any time, if multiple bits are set or
if the bits are in an invalid setting, these bits default to the 32
DWords setting.
N
o
t sup
ported
Cache Line Size
N
o
t sup
ported
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
7:6
RW
Not supported, must equal b‘00’.
5
RW
If ‘1’, Cache Line = 32 DWords.
4
RW
If ‘1’, Cache Line = 16 DWords.
3
RW
If ‘1’, Cache Line = 8 DWords.
2
RW
If ‘1’, Cache Line = 4 DWords.
1:0
RW
Not supported, must equal b‘00’.
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...