5. Configuration Registers
73
Tsi310 User Manual
80B6020_MA001_05
5.4.3
Command Register
This register provides a variety of configurable parameters defining the device’s interaction with
the PCI bus.
Address Offset
x‘04’
Access
See individual bit fields.
Reset Value
x‘0000’
Reserved
Fas
t Back-to-
B
ac
k Control
Sys
tem Err
o
r
Control
W
a
it C
y
cl
e
Control
Parity Error
Response
VGA Palette Snoop
C
ontrol
Me
mory W
rite
and
Inval
idate
Con
trol
S
p
ecial
Cycl
es C
ontrol
Bus Mas
ter
Control
M
e
mory S
p
ace Control
I/O S
p
ace
Co
ntro
l
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15:10
RO
Reserved
9
RO
Fast Back-to-Back Control
0 = Fast back-to-back transactions are allowed only for the same agent
This bit is ignored in PCI-X mode.
8
RW
System Error Control
0 = Disable the SERR# output driver.
1 = Enable the SERR# output driver.
7
RO
Wait Cycle Control
0 = Disable Address/Data stepping.
This bit is ignored in PCI-X mode.
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...