1. Functional Overview
20
Tsi310 User Manual
80B6020_MA001_05
Figure 1: Block Diagram
The Tsi310 is composed of the following major functional blocks (see
):
•
The device has two PCI-X interfaces. Each interface handles the PCI/PCI-X protocol for its
respective bus and depending on the type of transaction, can act as either a bus master or a
bus slave. These interfaces transfer data and control information flowing to and from the
blocks shown in the middle of the diagram.
•
Two phase-locked loops (PLLs), one for the primary clock domain and one for the
secondary clock domain. The PLL for each clock domain is used when that bus is running
in PCI-X mode; in PCI mode, the PLL is bypassed to allow the full frequency range as
defined by the bus architecture. The two bus clocks may be run synchronously or
asynchronously. A spread-spectrum clock input, within the architectural bounds, is
supported for either or both interfaces.
•
One set of configuration registers, programmable either from the primary or secondary
interface. The first 64 bytes of this address space conform to the architectural format for
bridge devices, called Header Type 1. The remaining 192 bytes are device-specific
registers. Each register is fully defined in
.
Primary PCI/PCI-X Bus
Secondary PCI/PCI-X Bus
80B6000_BK001_02
JTAG
Secondary
Bus Arbiter
Primary
Clock PLL
Secondary
Clock PLL
PCI-X
Interface
Bus
Master
Bus
Slave
PCI-X
Interface
Configuration Registers
Clocking & Reset
Data/Control Unit
Queue
Compare
Logic
Read Queue
8 entries
PW Queue
8 entries
Address
Decode
Control
Logic
Burst Read
Buffer
4 Kbytes
Posted Write
Buffer
1 Kbyte
Single Data
Phase Buffer
4 Bytes
Data/Control Unit
Queue
Compare
Logic
Read Queue
8 entries
PW Queue
8 entries
Address
Decode
Control
Logic
Burst Read
Buffer
4 Kbytes
Posted Write
Buffer
1 Kbyte
Single Data
Phase Buffer
4 Bytes
Bus
Slave
Bus
Master
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...