IDT PEB383 (QFN) User Manual Download Page 8

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1. Board Design

Tsi381 Evaluation Board User Manual

60E2000_MA001_03

Integrated Device Technology

www.idt.com

Figure 1: Evaluation Board Block Diagram

EEPROM

Tsi381

3.3V PCI 32-bit Connector

Slot 0

PCI

Power

Management

PCI Express Card Edge X1

PCIe

LA Probe

JTAG

Header

ATX Connectors

EEPROM

1x SerDes SMA

Points

SerDes Path

Resistor Select

Clock

Management

3.3V PCI 32-bit Connector

Slot 1

3.3V PCI 32-bit Connector

Slot 2

3.3V PCI 32-bit Connector

Slot 3

GPIO

Summary of Contents for PEB383 (QFN)

Page 1: ...eek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc Tsi381 Evaluation Board User Manual 60E2000_MA001_03 September 2009 ...

Page 2: ...MPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPECIAL DAMAGES HOWEVER THEY MAY ARISE AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES The code examples also may be subject to United States export control laws and ma...

Page 3: ...r Sequencing 13 1 4 4 System Power Design 13 1 4 5 PCI Vaux PCI Auxiliary Support 14 1 5 Clock Management 14 1 5 1 PCI 14 1 5 2 System Clock Distribution 15 1 6 Other Interfaces 15 1 6 1 JTAG Interface 15 1 6 2 EEPROM Interface 15 1 6 3 GPIO Interface 16 1 7 Hardware Reset 16 1 8 Logic Analyzer Connectivity 17 2 Configurable Options 19 2 1 Switches 19 2 1 1 DIP Switches 19 2 1 2 Push Button 23 2 2...

Page 4: ...Contents 4 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 4 3 P1 x1 PCIe Finger Connector 31 2 5 LEDs 31 3 Bill of Materials 33 ...

Page 5: ... Design Guidelines PCI Express Base Specification Revision 1 1 PCI Express CEM Specification Revision 1 1 PCI Express to PCI PCI X Bridge Specification Revision 1 0 Acronyms Revision History 60E2000_MA001_03 Formal September 2009 This document was rebranded as IDT It does not include any technical changes 60E2000_MA001_02 Formal September 2007 Added a new section that discusses PCI Vaux PCI Auxili...

Page 6: ...About this Document 6 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com ...

Page 7: ...0 Clock Management on page 14 Other Interfaces on page 15 Hardware Reset on page 16 Logic Analyzer Connectivity on page 17 1 1 Overview The key features of the Tsi381 evaluation board include the following see also Figure 1 Single x1 lane 2 5 Gbps PCIe 1 1 compatible riser card extended height form factor Four PCI slots 32 bit PCI bus 25 66 MHz operation PCI power support through system or externa...

Page 8: ...oard Block Diagram EEPROM Tsi381 3 3V PCI 32 bit Connector Slot 0 PCI Power Management PCI Express Card Edge X1 PCIe LA Probe JTAG Header ATX Connectors EEPROM 1x SerDes SMA Points SerDes Path Resistor Select Clock Management 3 3V PCI 32 bit Connector Slot 1 3 3V PCI 32 bit Connector Slot 2 3 3V PCI 32 bit Connector Slot 3 GPIO GPIO ...

Page 9: ...perating at 25 33 50 or 66 MHz 1 2 2 IDSEL Signals IDSEL signals are connected in the following order Slot 0 R A connector top slot 150 ohms to AD16 Device 0 Slot 1 150 ohms to AD17 Device 1 Slot 2 150 ohms to AD19 Device 3 Slot 3 150 ohms AD18 Device 2 1 2 3 Interrupt Signals The PCI interrupt signals are connected to the slots as shown in the following table 1 2 4 Pull up Signals The following p...

Page 10: ...or chain continuity 1 4 Power Management 1 4 1 Power Regulation The evaluation board s power regulation is implemented as follows Digital 3 3V power supply available from DC DC regulator or ATX supply Digital 1 2V switching regulator PCIe supplies filtered using EMI ferrite networks To support PCI cards the following additional power resources are included 12V to 5V DC DC converter 12V to 3 3V DC ...

Page 11: ... are a maximum of 25W slot Current limits are included in Table 4 The usage of the 12V supply provides access to the full 25W available from the system to the board The PCIe pinout design includes more 12V power pins as it allows more power per pin capability The evaluation board regulates all power from the 12V system rail however 3 3V from the system remains unused Table 3 Tsi381 Power Requireme...

Page 12: ...itions summarize the power available for a single PCI card without external supply An efficiency of 85 is taken into account for switching regulators These limits can be exceeded in cases where the system can provide more than the suggested limit which is usually only implemented in hot swap systems For additional slots or in cases where the system cannot supply enough power a separate ATX power c...

Page 13: ...e following list is a functional summary of the power design 1 Sequencing control over the following rails 3 3V PCI 3 3V Tsi381 I O PCIe AVDD 1 2V Tsi381 Core PCIe VDD 2 ATX 20 pin connector override which disables all power draw from the PCIe system Figure 2 System Power Distribution 3v3 5v DC DC Regulator TPS5124 PCIe System 12v ATX 20 pin 12v 12v 5v 3 3v Unused GND 1 2v DC DC 12V 3 3V 1 2V Powe...

Page 14: ...pports master and slave clocking for PCI Master When in master mode the Tsi381 generates the required PCI clock for all slots Slave When in slave mode an on board selectable 25 66 MHz clock generator is used On board resistor muxes are used to multiplex either Tsi381 s PCI clock or the external clock generator 1 5 1 1 PCIe For PCIe clocking a 100 MHz differential HCSL clock source is required The ...

Page 15: ...Wiggler connection 1 6 2 EEPROM Interface A single EEPROM device socket is available for programming the Tsi381 s registers during startup The socket is in an 8 pin DIP format Tip For more information about accessing the Tsi381 using JTAG see the JTAG Register Access Software Application Note ICS87604I PCIe System PCIe_REFCLK PCI Bus Connectors Tsi381 PCI_CLK CLKOUT 0 1 PCI_INT_CLK 0 PCI_EXT_CLK 0...

Page 16: ...owing list outlines the connections to GPIO External I O header J7 1 NC J7 2 GPIO0 J7 3 GPIO1 J7 4 GPIO2 J7 5 GPIO3 J7 6 Connected to ground LEDs D11 GPIO0 active led when driven low D1 GPIO1 active led when driven low D13 GPIO2 active led when driven low D12 GPIO3 active led when driven low 1 7 Hardware Reset The following figure shows the reset options of the Tsi381 evaluation board Figure 4 Boa...

Page 17: ...essage sent by the root complex No supporting hardware is necessary 1 8 Logic Analyzer Connectivity The serial buses have Midbus pads TMS818 probe for visibility of SerDes lines using a pre processor Each probing pad provides access to the RX and TX segments of a x1 link To access the PCI bus a Nexus PCI interposer card can be used with Tektronix mictor cables The card can be plugged into any PCI ...

Page 18: ...1 Board Design 18 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com ...

Page 19: ...e the following Switches on page 19 Shunt Jumpers on page 24 Debug Headers on page 26 Connectors on page 29 LEDs on page 31 2 1 Switches 2 1 1 DIP Switches Switches S1 to S6 combine four small slide switches identified with numbers 1 to 4 see Table 7 for individual switch definition Figure 5 DIP Switch Package Individual Switch Position ON OFF ...

Page 20: ...2 Configurable Options 20 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com Figure 6 Switch Locations SW2 S3 S4 SW1 S5 S6 S1 ...

Page 21: ...y Table 8 contains the clock frequency settings for S3 Table 7 S1 Settings Switch Number Description Default Setting On Off Setting 1 M66EN ON ON Connects M66EN to all cards OFF Forces M66EN high if S1 2 OFF 2 M66EN OFF ON Forces M66EN to GND OFF Disables forcing M66EN to GND Table 8 S3 Settings Switch Number Description Default Setting On Off Setting 1 DIV_SEL0 OFF FBDIV_SEL1 FBDIV_SEL0 DIV_SEL1 ...

Page 22: ...LL is reference clock from connector J10 OFF Clock source for PLL is a 25 MHz oscillator 3 PLL select OFF ON PLL is bypassed OFF PLL is enabled External clock source is multiplied as per S3 setting 4 No function Table 10 S5 Settings Switch Number Description Default Setting On Off Setting 1 No Function 2 PCIe on board PLL enable ON ON On board PCIe reference clock PLL is disabled OFF On board PCIe...

Page 23: ... evaluation board is powered up with a stand alone ATX power supply SW2 is used to reset the evaluation board When pushing the reset button the board is reset the same way a PCIe system reset would reset the board Table 11 S6 Settings Switch Number Description Default Setting On Off Setting 1 No function 2 Internal arbiter option ON ON Internal arbiter is enabled OFF Internal arbiter is disabled 3...

Page 24: ... Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 2 Shunt Jumpers Shunt jumpers control special features on the evaluation board see Figure 7 These jumpers are explained in the following sub sections Figure 7 Shunt Jumper Locations J21 J6 ...

Page 25: ... On Off push button to enable the ATX power supply 2 2 2 J21 Shunt Jumper J21 is used to force the Tsi381 into a special debug mode The default setting for this jumper is ON Table 12 J6 Shunt Jumper Setting Jumper Setting Default Setting Function Installed Removed Forces ATX power supply ON Removed Normal operation ATX power supply is turned On OFF from push button ...

Page 26: ...on Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 3 Debug Headers Debug headers are used to connect to signals on the evaluation board This section provides header pinouts Figure 8 Debug Header Locations J23 J22 ...

Page 27: ...grated Device Technology www idt com 2 3 1 J22 Tsi381 JTAG Table 13 J22 Pin Assignment Pin Number Signal Assignment Pin Location 1 TDO 2 NC 3 TDI 4 3 3V 5 NC 6 3 3V 7 TCK 8 NC 9 TMS 10 NC 11 NC 12 GND 13 NC 14 NC 15 NC 16 GND 1 7 5 9 3 2 4 6 8 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ...

Page 28: ...e 14 J23 Pin Assignment Pin Number Signal Assignment Pin Location 1 PCIE_RXD_EDG_P0 2 GND 3 PCIE_RXD_EDG_N0 4 PCIE_TXD_EDG_P0 5 GND 6 PCIE_TXD_EDG_N0 7 N C 8 GND 9 N C 10 N C 11 GND 12 N C 13 N C 14 GND 15 N C 16 N C 17 GND 18 N C 19 N C 20 GND 21 N C 22 N C 23 GND 24 N C 1 7 5 9 3 2 4 6 8 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ...

Page 29: ...urable Options 29 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com 2 4 Connectors Figure 9 Board Connector Locations P1 J3 J2 Slot 0 J36 Slot 1 J1 Slot 2 J37 Slot 3 ...

Page 30: ...ignments are as per the PCI standard for 32 bit connectors 2 4 2 J3 ATX Power Connector A standard ATX power supply can be used to power up the board when used stand alone not plugged into a PCIe system Table 15 J3 Pin Assignment Pin Number Signal Assignment J3 Pin Location 1 3 3V 2 3 3V 3 GND 4 5V 5 GND 6 5V 7 GND 8 N C 9 5VSB 10 12V 11 3 3V 12 12V 13 GND 14 GND 15 GND 16 GND 17 GND 18 N C 19 5V ...

Page 31: ...A001_03 Integrated Device Technology www idt com 2 4 3 P1 x1 PCIe Finger Connector The pin assignment for the finger connector is as per the PCIe standard Note that the JTAG signals TDI and TDO are connected together on the board 2 5 LEDs Figure 10 LED Locations D2 D8 D18 ...

Page 32: ...2 Configurable Options 32 Tsi381 Evaluation Board User Manual 60E2000_MA001_03 Integrated Device Technology www idt com ...

Page 33: ...X CAPC0603 X5R CER SMT 0 1UF 10 25V 0603 5 C10 C62 C110 C140 C162 0402ZC103KAT2A 0402ZC103KAT2A AVX CAPC0402 X7R CER SMT 0 01UF 10 10V 0402 113 C17 21 C23 25 C38 C48 49 C52 C60 61 C63 65 C72 C105 C108 109 C114 115 C117 127 C130 139 C141 142 C144 161 C163 164 C166 171 C175 177 C179 C182 186 C189 198 C200 203 C206 207 C211 C220 221 C226 228 C233 C252 260 0402ZD104KAT2A 0402ZD104KAT2A AVX CAPC0402 X5...

Page 34: ...NTINTED DIFFUSED 1 D9 B220A 13 F DIODES INC DIOSMA 2A SCHOTTKY DIODE RECTIFIER0 5VF 1 D10 S1B S1B FAIRCHILD DIOSMA GENERAL PURPOSE RECTIFIER 1 D23 LCDA15C 1 TC SEMTECH SOT143 TVSDIODEARRAY 1 F1 R154 010 R154 010 LITTLEFUSE FUSE_154 SMT FUSE BLOCK FOR FAST 10A FUSE INCLUDED 5 FB1 2 FB4 BLM18AG601SN1D BLM18AG601SN1D MURATA FB_0603 SMT FERRITE BEAD 60OHMS 25 0 2AMPS 0603 FB7 8 2 FB3 FB6 BLM31PG500SN1...

Page 35: ...03 5 R9 12 R209 ERJ 3GEYJ242V ERJ 3GEYJ242V PANASONIC RESC0603 RES SMT 2 4K OHM 0 1W 5 0603 18 R13 R52 ERJ 3EKF1001V ERJ 3EKF1001V PANASONIC RESC0603 RES SMT 1K OHM 0 1W 1 0603 R83 R86 87 R91 R93 R95 R100 R114 117 R136 R172 173 R259 R264 26 R14 25 R53 R85 R118 R120 R137 R157 R187 R198 R207 R226 R241 242 R256 R283 ERJ 3GEYJ822V ERJ 3GEYJ822V PANASONIC RESC0603 RES SMT 8 2K OHM 0 1W 5 0603 3 R32 R48...

Page 36: ...475 OHM 0 1W 1 0603 1 R121 ERJ 3GEYJ473V ERJ 3GEYJ473V PANASONIC RESC0603 RES SMT 47K OHM 0 1W 5 0603 2 R122 R138 WSL2010R1000FE A VISHAY RESC2010 RES SMT 0 100 OHM 0 5W 1 2010 CURRENTSENSE 1 R132 ERJ 3EKF7151V ERJ 3EKF7151V PANASONIC RESC0603 RES SMT 7 15K OHM 0 1W 1 0603 1 R142 ERJ 3EKF1502V ERJ 3EKF1502V PANASONIC RESC0603 RES SMT 15 0K OHM 0 1W 1 0603 7 R153 R156 R158 R288 R293 295 ERJ 3GEYJ20...

Page 37: ... 65VTO5 5V 1 U5 SN74LVC1G14DBV T SN74LVC1G14DBV T TI SOT23 5 SINGLE SCHMITT TRIGGER INVERTER 1 U6 ICS87604AGI ICS87604AGILF IDT TSOP65P81 28 LOW VOLTAGE LOW SKEW 1 4 PCI PCI X ZERO DELAY CLOCK GENERATOR 1 U7 CY2305SXC 1H CYPRESS SOIC127P600 8 1 TO 4 3 3V ZERO DELAY CLOCKBUFFER 4 U8 U13 U17 U31 MAX4372FEUK T MAX4372FEUK MAXIM SOT23 5 VOLTAGE OUTPUT HIGH SIDE CURRENT SENSE AMPLIFIER WITH 50V V GAIN ...

Page 38: ...MOS COMPARATOR R TO R INPUT OPEN DRAINOUTPUT 1 U33 EL7532IYZ INTERSIL TSSOP50P49 10 MONOLITHIC 2A STEP DOWN REGULATOR 1 5MHZ 2 6 5V IN 0 8 TO VIN OUT 2 Y1 2 HCM4925 000MAB JT HCM4925 000MAB J UT CITIZEN XTAL_HCM4925_0 00MABJT 25MHZ CRYSTAL 18PF 30PPM CAL TOL 50PPM TEMP TOL a IDT used Pb free parts where available Table 16 Bill of Materials Continued Qty Reference Designator Part Numbera Part Numbe...

Page 39: ...er products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license...

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