IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 73 / 744

IDT Reset and Initialization
PES32NT24xG2 User Manual 3 - 9 January 30, 2013
Notes
• PxACTIVEN and PxLINKUPN are negated.
– All input signals associated with the port are ignored and have no effect on the operation of the
device.
• The state of the following hot-plug input signals is ignored: PxAPN, PxMRLN, PxPDN, PxPFN,
and PxPWRGDN.
– The port is not associated with a PCI Express link. PCI Express configuration requests targeting
the port are not possible and the port is not part of the PCI Express hierarchy.
– The port is not associated with any switch partition. The port is unaffected by the state of any
switch partition, and vice-versa.
– Unused logic is placed in a low power state.
– All registers associated with the port remain accessible from the global address space.
1
– The port remains in this state regardless of the setting of the port’s operating mode (i.e., via the
port’s SWPORTxCTL register).
An activated port behaves as described throughout the rest of this manual and may be configured in one
of several operating modes, as described in Chapter 5.
Static Configuration of a Stack
A stack may be configured statically using the corresponding Stack Configuration (STKxCFG) pins.
These pins are sampled by the switch as part of the boot-configuration vector during switch fundamental
reset. The STKxCFG pins determine the initial value of the STKCFG field in the corresponding STKxCFG
register. The encoding of the STKxCFG pins is identical to that of the STKCFG field shown in Tables 3.4
through 3.7.
– For Stacks 0 and 1, the STKxCFG pins have 2 bits each (i.e., STK0CFG[1:0] and STK1CFG[1:0]).
These bits correspond to the two least significant bits of the STKCFG field in the corresponding
STKxCFG register. Therefore, for these stacks, configurations 0x0 through 0x3 may be selected
statically. Other configurations must be selected dynamically (see section Dynamic Reconfigura-
tion of a Stack via EEPROM / SMBus below).
– For Stacks 2 and 3, the STKxCFG pins have 5 bits each. Therefore, all 26 possible configurations
may be selected statically.
– Note that for all stacks the STKxCFG[2] pin can be used to select between a stack configuration
and its mirror image. For example, when the STKxCFG pins are set to 0b00010, the stack is
configured per configuration 0x2 (ports are configured as x4, x2, x2). The setting 0b00110 yields
the mirror image which corresponds to stack configuration 0x6 (ports are configured as x2, x2, x4).
Dynamic Reconfiguration of a Stack via EEPROM / SMBus
In addition to static configuration as described above, each stack may be reconfigured via the EEPROM
or SMBus slave interface during the switch fundamental reset sequence (i.e., at the EEPROM loading step
or via the slave SMBus interface when the ports are in quasi-reset state
2
).
Dynamic reconfiguration of a stack requires the following procedure.
1. The operating mode of all ports associated with the stack must be set to disabled (see Chapter 5,
Switch Partition and Port Configuration).
2. The stack must be reconfigured by programming the STKCFG field in the corresponding STKxCFG
register.
3. The operating mode of the ports associated with the stack must be set as desired. For example,
some ports in the stack may be set to operate in downstream switch mode, others in upstream
switch mode, and others may remain disabled.
Dynamic reconfiguration of a stack through other methods (i.e., through PCI Express configuration
requests or via SMBus after the fundamental reset sequence completes) is not supported.
1.
Refer to Chapter 19, Register Organization, for details on the switch’s global address space.
2.
Refer to section section Switch Fundamental Reset on page 3-2 for details on the quasi-reset state.