IDT EB4T4 Eval Board, Manual

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IDT Installation of the EB4T4 Eval Board
EB4T4 Eval Board Manual 2 - 7 a
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I
2
C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consist of an SMBus clock pin and SMBus data pin.
SMBus Master Interface
Connected to the master SMBus interface are four 16-bit I/O Expanders (PCA9555) and a serial
EEPROM (24LC512). Four I/O Expanders are used as the interface for the onboard hot-plug controllers
(MIC2591B). The Master SMBus interface provides connection to the external serial EEPROMs used for
initialization and the I/O expander used for hot-plug signals.
The bus address for the selected EEPROM device is
0b1010011
by default.
The PES4T4 provides a JTAG connector J4 for access to the PES4T4 JTAG interface. The connector is
a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.9 for the JTAG Connector J2 pin out.
Attention Buttons
The PES4T4 features four attention buttons, shown in Table 2.10. Each button corresponds to a partic-
ular port and is used to initiate hot-swapping events.
Signal Description Default
S3[4] CCLKDS OFF
S3[5] CCLKUS OFF
S5[6] RSTHALT ON
S5[1] SWMODE[0] ON
S5[2] SWMODE[1] ON
S5[3] SWMODE[2] ON
S5[5] APWRDIS# ON
Table 2.6 Boot Configuration Vector Switches S3 and S5 (ON=0, OFF=1)
JTAG Connector J2
Pin Signal Direction Pin Signal Direction
1 /TRST - Test reset Input 2 GND —
3 TDI - Test data Input 4 GND —
5 TDO - Test data Output 6 GND —
7 TMS - Test mode select Input 8 GND —
9 TCK - Test clock Input 10 GND —
Table 2.7 JTAG Connector Pin Out