3. RapidIO Lanes > Lane to Port Mapping
CPS-1848 User Manual
70
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
3.1
Lane to Port Mapping
As displayed in
, each S-RIO port can be comprised of one, two, or four lanes (this is called port width). After a device
reset, the CPS-1848’s port width settings and lane to port mapping are configured based on the setting of the QCFG[7:0] pins
(for more information, see the CPS-1848 Datasheet).
Software can also control the device’s port width settings and lane to port mapping using the
Quadrant Configuration Register
shows the supported mapping of lanes to ports for each CPS-1848 quadrant based on the value of the QUADx_CFG
field in the
Quadrant Configuration Register
.
Table 20: Lane to Port Mapping
1
QUADx_CFG /
QCFG
2
Setting
PLL
Port Width
Mapping
Port
Lane(s)
Quadrant 0 / QCFG[1:0]
00
0
4x
0
0–3
4
4x
4
16–19
8
4x
8
32–35
-
-
12, 16 (Unused)
-
01
0
2x
0
0–1
0
2x
12
2–3
4
4x
4
16–19
8
4x
8
32–35
-
-
16 (Unused)
-
10
0
2x
0
0–1
0
2x
12
2–3
4
4x
4
16–19
8
2x
8
32–33
8
2x
16
34–35
11
0
2x
0
0–1
0
1x
12
2
0
1x
16
3
4
4x
4
16–19
8
4x
8
32–35
