10. Registers > Global Device Configuration Registers
CPS-1848 User Manual
366
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
10.14.16 Quadrant Configuration Register
This register configures the port width and lane to port mapping of the CPS-1848’s quadrants. The following register table
shows the port width configuration based on the value of the QUADx_CFG field. For lane to port mapping based on the value
programmed into the same field, see
.
Before changing this register, see
Port Reconfiguration Operations
for the correct procedure to follow.
Register Name: QUAD_CFG
Reset Value: Undefined
Register Offset: 0xF20200
Bits
0
1
2
3
4
5
6
7
00:07
Reserved
08:15
Reserved
16:23
Reserved
24:31
QUAD3_CFG
QUAD2_CFG
QUAD1_CFG
QUAD0_CFG
Bits
Name
Description
Type
Reset
Value
0:23
Reserved
Reserved
RO
0
24:25
QUAD3_CFG
0b00 = 3 by 4x ports
0b01 = 2 by 4x, 2 by 2x ports
0b10 = Undefined
0b11 = Undefined
Note: The initial value of this field is determined by the setting of
the QCFG[7:6] external pins.
RW
Undefined
26:27
QUAD2_CFG
0b00 = 3 by 4x ports
0b01 = 2 by 4x, 2 by 2x ports
0b10 = Undefined
0b11 = Undefined
Note: The initial value of this field is determined by the setting of
the QCFG[5:4] external pins.
RW
Undefined
28:29
QUAD1_CFG
0b00 = 3 by 4x ports
0b01 = 2 by 4x, 2 by 2x ports
0b10 = 1 by 4x, 4 by 2x ports
0b11 = 2 by 4x, 1 by 2x, 2 by 1x ports
Note: The initial value of this field is determined by the setting of
the QCFG[3:2] external pins.
RW
Undefined
