IDT 89HPES16NT2, User Manual

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IDT SMBus Interfaces
PES16NT2 User Manual 6 - 4 April 15, 2008
Notes
Master SMBus Interface
The master SMBus interface is used during a fundamental reset to load configuration values from an
optional serial EEPROM.
Initialization
Master SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page
2-7). During a fundamental reset initialization sequence, the state of the Master SMBus Slow Mode
(MSMBSMODE) signal is examined. If this signal is asserted, the Master SMBus Clock Prescalar
(MSMBCP) field in the port A SMBus Control (PA_SMBUSCTL) register is initialized to support 100 KHz
SMBus operation. If the signal is negated, then the MSMBCP field is initialized for 400 KHz SMBus opera-
tion.
Serial EEPROM
During a fundamental reset, an optional serial EEPROM may be used to initialize any software visible
register in the device. Serial EEPROM loading occurs if the Switch Mode (SWMODE[3:0]) field selects an
operating mode that performs serial EEPROM initialization (e.g., transparent mode with serial EEPROM
initialization and non-transparent mode with serial EEPROM initialization).
The address used by the SMBus interface to access the serial EEPROM is specified by the
MSMBADDR[4:1] signals as shown in Table 6.3.
Device Initialization from a Serial EEPROM
During initialization from the optional serial EEPROM, the master SMBus interface reads configuration
blocks from the serial EEPROM and updates corresponding registers in the PES16NT2. Any PES16NT2
software visible register in the upstream port, downstream port(s), and internal side of the non-transparent
bridge may be initialized with values stored in the serial EEPROM.
Each software visible register in the PES16NT2 has a CSR system address which is formed by adding
the PCI configuration space offset value of the register to the base address of the configuration space in
which the register is located. Configuration blocks stored in the serial EEPROM use this CSR system
address shifted right two bits (i.e., configuration blocks in the serial EEPROM use doubleword CSR system
addresses and not byte CSR system addresses). Base addresses for the PCI configuration spaces in the
PES16NT2 are listed in Table 6.4. While there is no direct accesses to non-transparent bridge external
endpoint registers, these register may be initialized by using the external non-transparent bridge configura-
tion window located in the configuration space of the internal non-transparent bridge endpoint.
Address
Bit
Address Bit Value
1 MSMBADDR[1]
2 MSMBADDR[2]
3 MSMBADDR[3]
4 MSMBADDR[4]
5 1
6 0
7 1
Table 6.3 Serial EEPROM SMBus Address