1531Da RevA 6/13/00
Copyright © 2000 Integrated Circuit Systems, Inc. All rights reserved.
June, 2000
2
Chapter 1
Daughterboard Layouts
ICS1531 Daughterboard - Preliminary
Chapter 1
Daughterboard Layouts
Figure 1-1
shows the location of the components used to configure the LVDS Daughterboard. (For both a
figure of the ICS1531 Demo Board and an LCD interconnect table, see the
ICS1531 Demo Board
Guide
.)
Figure 1-1.
LVDS Daughterboard for ICS1531 Demo Board
Table 1-1
lists and describes components on the LVDS Daughterboard, a schematic for which is in
Chapter
3, “Schematics”
. For the LVDS daughterboard, the input is digital (2 pixels/clock) and the output is
low-voltage digital signals (2 pixels/clock).
Table 1-1.
LVDS Daughterboard Components
Component #
and Label (If Any)
Component Name, Function, and Settings
H6, H7, H8
Header 6, 7, and 8.
Headers that connect the LVDS Daughterboard to the following signals from the
ICS1531 Demo Board:
•
Input digital panel data that is output from ICS1531 Demo Board U1 (ICS1531)
•
Clock signals from ICS1531 Demo Board U2 (Xilinx XC95144XL):
– H6 - clock signals are on pins PX and PY (two programmable control signals).
– H7 - clock signals are on pins PHS (panel HSYNC) and PVS (panel VSYNC).
– H8 - clock signals are on pins CLK (clock) and DE (display enable).
LT1086CT
Integrated Circuit Systems, Inc.
LVDS
ICS1531 DEMO BOARD REV C
COPYRIGHT © 2000
R
A
1
R
A
3
G
R
A
5
R
A
7
G R
B
1
R
B
3
G R
B
G
R
B
7
P
Y
B
A
1
B
A
3
G
B
A
5
B
A
7
G B
B
1
B
B
3
G B
B
5
G
B
B
7
D
E
H6
H8
G
A
1
G
A
3
G
G
A
5
G
A
7
G G
B
1
G
B
3
G G
B
5
G
G
B
7
P
V
S
H7
B
A
0
B
A
2
G
B
A
4
B
A
6
G
B
B
0
B
B
2
G
B
B
4
G
B
B
6
C
L
K
G
A
0
G
A
2
G
G
A
4
G
A
6
G
G
B
0
G
B
2
G
G
B
4
G
G
B
6
P
H
S
R
A
0
R
A
2
G
R
A
4
R
A
6
G
R
B
0
R
B
2
G
R
B
4
G
R
B
6
P
X
U14
JP8
3V
5V
U13
JP10
U15
JP7
+12V
+5V
JP9
1
2
29
30
Serial
Number
Alternative
Connector
3
2
V
5
/
V
3
.3
4
G
N
D
6
T
X
O
0
-
8
T
X
O
1
-
1
0
T
X
O
2
-
1
2
T
X
O
3
-
1
4
T
X
O
C
k
-
1
6
G
N
D
1
8
T
X
E
0
-
2
0
T
X
E
1
-
2
4
T
X
E
3
-
2
2
T
X
E
2
-
2
6
T
X
E
C
k
-
JP9
V
5
/
V
3
.3
1
G
N
D
3
T
X
O
0
+
5
T
X
O
1
+
7
T
X
O
2
+
9
T
X
O
3
+
1
1
T
X
O
C
k
+
1
3
G
N
D
1
5
T
X
E
0
+
1
7
T
X
E
1
+
1
9
T
X
E
3
+
2
3
T
X
E
2
+
2
1
T
X
E
C
k
+
2
5
G
N
D
2
7
V
1
2
2
9
2
8
G
N
D
3
0
V
1
2
