User Interface
Figure 1 shows a Block Diagram of
the VXI-5524 and the User's Interface.
The VXI-5524 provides the user with 48
Digital I/O lines, a Data Expansion Bus,
a VXIbus interrupt and TTL Trigger
lines. The 48 Digital I/O lines are con-
figurable as inputs or outputs in 16 line
groups by setting bits in the VXI-5524's
Configuration Register. As outputs, each
line can sink 40 mA or source 20 mA to
drive most any TTL/CMOS compatible
device. When configured as inputs, each
line is a high impedance TTL gate with
a 33 Kohm pullup to 5 Vdc for sensing
open collector lines, contact closures or
TTL/CMOS level signals.
The Data Expansion Bus is a 16 bit
wide bus that extends the unused VXI
register addresses and data lines to the
user's circuits. Examples in the manual
show how to decode the address lines
and connect registers, FIFOs and other
circuits to the Data Expansion Bus.
The VXI-5524 extends a selected
pair of TTL Trigger lines to the user's
interface. The TrigIn# line can be used
to initiate an action such as data capture,
data conversion, etc. in the user's cir-
cuits. The TrigOut# line can be used to
pulse a VXIbus TTL Trigger line and
initiate action in another module.
The VXI-5524 has an IRQ input that
latches three Cause code lines when
pulsed. The Cause lines are new with
the VXI-2 Specification and gives a reg-
ister-based device a way of communi-
cating the cause of the interrupt when it
is queried by the Slot 0 Controller. VX-
Ibus IRQ line selection and interrupt
enable is controlled by bits set in the
new Interrupt Control Register.
The VXI-5524 passes all seven VX-
Ibus voltages and a 10 MHz clock on to
the user's interface. The user can select
either the VXI-5524's internal 10 MHz
oscillator or the VXIbus ECL 10 MHz
clock as the clock source.
VXI-5524 Register Map
Figure 2 shows the VXI-5524's reg-
ister map. Each VXIbus module is as-
signed 32 (16-bit) register addresses in
the VXI A16 address space. The register
addresses values in Figure 2 are offsets
from the module's logical address. i.e.
The Device Type Register is 0x02 HEX
which is the module's logical address
plus 2.
VXI-5501/VXI-5502 DESCRIPTIONS
Bus
Xcvr
Three
16-bit
Bi-dir
Latch
VXIbus
User's Interface
Data
Xcvr
Trigger
Selector
Bi-directional TTL Trigger Pair
IRQ
Selector
VXI Interrupt and Cause Code Lines
16-bit Data
Expansion Bus
48 Data Lines
VXI Control, Status
and ID Registers
Address
Decoder
VD(15:0)
Handshake Lines
VXIbus Power and Clocks
Address Lines
and Strobes
TTLTRG0-7
IRQ1-7
+5, -5, -2,
±
12,
±
24V
Configuration
Processor
and Memory
10MHz
Oscillator
Figure 1 VXI-5524 Block Diagram
Figure 2 VXI-5524 Register Map
The lower 16 register addresses
are used for the VXIbus interface, the
upper 16 register address are for the
device. The VXI-5524 uses the top three
register addresses for the Digital I/O
lines. Register addresses 0x20 through
0x38 are made available to the user's
circuits with the Data Expansion Bus.
The Configuration and Interrupt
Control registers configure the Digital
I/O lines and control the Trigger and
Interrupt operation. The ID, Type,
Serial Number and Version registers
identify the VXI module and its capabil-
ity. The user can change these registers
to configure the interface and personal-
ize the finished module as his product .
All register values are then saved in an
EEPROM on the VXI-5524 and are auto-
matically recalled at power turn-on time
or when the board is reset.
3E
Digital I/O Reg-CH 48:33
R/W
3C
Digital I/O Reg-CH 32:17
R/W
3A
Digital I/O Reg-CH 16:1
R/W
38
36
34
32
30
Data Expansion
2E
Bus Area
2C
2A
28
26
24
22
20
1E
Sub Class
R
1C
Interrupt Control
R/W
1A
Interrupt Status
R
18
16
Reserved by
14
VXI-2 Specification
12
10
0E
Version Number
R
0C
(Serial Number Lo)
0A
Serial Number Hi
R
08
Attribute Register
R
06
Configuration Processor
W (8 bits only)
04
Status/Control
R/W
02
Device Type
R
00
ID/(Logical Address)
R
R e g A d d r R e g i s t e r U s e
