41
8.2 Support
In the CardBus standard adopted by PC Card 95, the data
transfer bus was extended to 32bit and bus clock became 33MHz.
Since the busmaster mode is also implemented, CardBus is
suitable for high performance required multimedia cards such as
fast LAN Card, VIDEO Card or graphic processing cards. With the
ZV Card such as MPEG cards, Multimedia environment will be
easily realized.
16-bit PC Card control interface signals, controlled by the
timing synthesizer circuit, are programmable so that not only timing
requirement of 16-bit PC Card compliant with PCMCIA2.1/
JEIDA4.2 but also faster timing requirement than it is available.
Recognition of CardBus or 16-bit PC Card is examined
automatically when cards are inserted, and the card control
interface will be composed properly on the result of recognition. So,
CardBus card and 16-bit PC Card are available simultaneously
8.3 Software Support
8.3.1 OS Support
[Windows 98]
R5C475II is fully supported by Windows 98.
8.3.2 R5C475II Installation
[
Windows 98]
No configuration is necessary except the general setting of
BIOS. (4.3)
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Appendix A. Watch-Dog Timer
The WatchDog Timer is a device to ensure that standalone
systems can always recover from catastrophic conditions that
cause the CPU to crash. This condition may have occurred by
external EMI or a software bug. When the CPU stops working
normally, hardware on the board will perform hardware reset (cold
boot) to bring the system back to a known state.
Three I/O ports control the WatchDog Timer.
543
Write
Set Watch-Dog Time period
543
(hex)
Read
Enable the refresh the WatchDog Timer.
143/943
(hex)
Read
Disable the WatchDog Timer.
Prior to enable the WatchDog Timer, user has to define Timer
first. The output data is a value of time interval and the range of
the value is from 01(hex) to FF (hex) and time interval 1 sec to 255
sec.
Data
Time Interval
01 1
sec
02 2
sec
03 3
sec
04 4
sec
.
.
.
.
.
.
FF 255
sec
This will enable and activate the countdown timer which will
eventually time out and reset the CPU to ensure that this reset
condition does not occur, the Watch-Dog Timer must be
periodically refreshed by reading the same I/O port 143/943H and
