4
6.1 Introduction .....................................................................46
Appendix A. Watchdog Timer ...................................... 47
Appendix B. I/O Address Map ...................................... 50
B.1 System I/O Address Map.................................................50
B.2 DMA channel assignments ..............................................51
B.3 Interrupt assignments ......................................................51
B.4 1
st
MB memory map ........................................................52
Summary of Contents for WAFER-5823
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