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Advanced Chipset Features
DRAM Timing By SPD Enabled
DRAM Clock 133M
SDRAM Cycle Length 3
Bank Interleave Disabled
Memory Hole Disabled
PCI Master Pipeline Req Enabled
P2C/C2P Concurrency Disabled
Fast R-W Turn Around Disabled
System BIOS Cacheable Disabled
Video BIOS Cacheable Disabled
Frame Buffer Size 8M
AGP Aperture Size 64MB
Power-supply Type AT
OnChip USB Disabled
USB Keyboard Support Disabled
OnChip Sound AUTO
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
PCI Master 0 WS Write Enabled
Item Help
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Menu Level
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Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should
never need to be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
DRAM Timing By SPD
This item allows you to select the value in this field, depending on whether the
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board has paged DRAMs or EDO (extended data output) DRAMs.
The Choice:
Enabled, Disabled.
DRAM Clock
This item allows you to control the DRAM speed.
The Choice: CPU FSB 200MHz(133/100MHz) ;
CPU FSB 266MHz(133MHz)
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified by the system designer.
The Choice: 2, 3.
Memory Hole
In order to improve performance, certain space in memory is reserved for ISA
cards. This memory must be mapped into the memory space below 16MB.
The Choice: 15M-16M, Disabled.
P2c/C2P Concurrency
This item allows you to enable/disable the PCI to CPU, CPU to PCI concurrency.
The choice: Enabled, Disabled.
System BIOS Cacheable
Selecting
Enabled
allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
The Choice: Enabled, Disabled.
Vedio RAM Cacheable
Select Enabled allows caching of the video RAM , resulting in better
system performance. However, if any program writes to this memory
area, a system error may result. The choice: Enabled, Disabled.
OnChip USB
