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NOVA-3710/3710SV Socket 370 Celeron
TM
& Pentium III
®
Multimedia & Dual VGA , Ethernet Embedded Board
47
Advanced DRAM Control 1 Press Enter
Advanced DRAM Control 2 Press Enter
System BIOS Cacheable Disabled
Video BIOS Cacheable Disabled
Memory Hole At 15M-16M Enabled
AGP Aperture Size 64MB
Graphic Window WR Combin Enable
Concurrent function ( MEM ) Enabled
Concurrent function ( PCI ) Enabled
CPU Pipeline Control Enabled
PCI Delay Transaction Enabled
Power-supply Type AT
Memory Parity Check Enabled
Item Help
_______________________
____________
Menu Level
¾
↑↓←→
Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit
F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized
Defaults
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional ISA
bus and the PCI bus. It must be stated that these items should never
need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system.
Advanced DRAM Control 1 / 2 Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully chosen
and should only be altered if data is being lost. Such a scenario might
well occur if your system had mixed speed DRAM chips installed so that
greater delays may be required to preserve the integrity of the data held
in the slower memory chips.
Auto Configuration
Summary of Contents for NOVA-3710
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