4.2.3.4
The status register
Address
10h
is used by the status register. Reading from this address will get the
data from the status register. The format of status register is:
Bit7-6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Gain
Control
8245
Timer 1
8245
Timer 0
8245
Timer 2
Reserved
Analog
input type
A/D ready
Bit 7-6:
Current A/D gain control.
Bit 5 :
Output of 8254 timer 1.
Bit 4 :
Output of 8254 timer 0.
Bit 3 :
Output of 8254 timer 2.
Bit 2 :
Reserved. Used for hardware testing.
Bit 1 :
Analog input type, ‘1’ indicates that analog input type is single-
ended and ‘0’ indicates analog input is differential.
Bit 0 :
A/D ready signal. ‘0’ indicates not ready, A/D is under conversion.
‘1’ indicates ready, A/D is completely converted and is idle now.
4.2.3.5
The A/D software trigger register
Writing to this port (
1Ch
) will generate an A/D trigger pulse signal.
Note:
Although a very fast trigger can be performed (more than the speed of A/D
controller, 110 K) via this method, a reasonable delay time should be left
between the two triggers.
A/D
Busy
Software
trigger
8
μ
s
Delay time
Conversion Tim
e
Figure 4-1: Software trigger delay time.
PCI-1002 Series User Manual (Ver.2.8, Oct. 2011, PMH-015-28)
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