4 - 3
4-2-4 POWER AMPLIFIER CIRCUIT (MAIN unit)
The power amplifier circuit amplifies the driver signal to an
output power level.
The RF signal from the pre-drive amplifier (Q8) is applied to
the power module (IC3) to obtain 25 W for IC-F610/F620, or
45 W for IC-F621 of RF power.
The amplified signal is passed through the antenna switch-
ing circuit (D2), low-pass filter and APC detector, and is then
applied to the antenna connector.
Control voltage for the power amplifier (IC3, pin 3) comes
from the APC amplifier (IC2) to stabilize the output power.
The transmit mute switch (D32) controls the APC amplifier
when transmit mute is necessary.
4-2-5 APC CIRCUIT (MAIN unit)
The APC circuit protects the power amplifier from a mis-
matched output load and stabilizes the output power.
The APC detector circuit detects forward signals and reflec-
tion signals at D11 and D1 respectively. The combined volt-
age is at minimum level when the antenna impedance is
matched at 50
Ω
, and is increased when it is mismatched.
The detected voltage is applied to the APC amplifier (IC2,
pin 3), and the power setting “T4” signal from the D/A con-
verter (IC7, pin 4), controlled by the CPU (IC20), is applied
to the other input for reference. When antenna impedance is
mismatched, the detected voltage exceeds the power set-
ting voltage. Then the output voltage of the APC amplifier
(IC2, pin 4) controls the input current of the power module
(IC3) to reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programable divider.
The PLL circuit contains the TX/RX VCO circuit (Q14, Q13).
The oscillated signal is amplified at the buffer amplifiers
(Q11, Q12) and then applied to the PLL IC (IC4, pin 5) via
the low-pass filter (L32, C298, C299).
The PLL IC contains a prescaler, programable counter, pro-
gramable divider and phase detector, etc. The entered sig-
nal is divided at the prescaler and programable counter sec-
tion by the N-data ratio from the CPU. The reference signal
is generated at the reference oscillator (X2) and is also
applied to the PLL IC. The PLL IC detects the out-of-step
phase using the reference frequency and outputs it from
pin 9. The output signal is passed thorough the loop filter
and is then applied to the VCO circuit as the lock voltage.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUIT
The VCO circuit contains a separate RX VCO (Q13, D16)
and TX VCO (Q14, D17, D18). The oscillated signal is ampli-
fied at the buffer amplifiers (Q11, Q10) and is then applied to
the T/R switch circuit (D14, D15). Then the receive 1st LO
(Rx) signal is applied to the 1st mixer (Q3) and the transmit
(Tx) signal to the YGR amplifier circuit (Q9).
A portion of the signal from the buffer amplifier (Q11) is fed
back to the PLL IC (IC4, pin 5) via the buffer amplifier (Q12)
and low-pass filter (L32, C298, C299) as the comparison
signal.
• PLL circuit
Shift register
×
3
Prescaler
Phase
detector
Loop
filter
Programable
counter
Programable
divider
X2
15.3 MHz
45.9 MHz signal
to the FM IF IC
16
Q13, D16
RX VCO
TX VCO
Buffer
Buffer
Buffer
Q10
Q12
Q11
Q34
19
18
17
PLST
IC4 (PLL IC)
SO
SCK
to transmitter circuit
to 1st mixer circuit
D15
D14
8
5
Q14, D17, D18
LPF
