4-4 POWER SUPPLY CIRCUITS
4-4-1 VOLTAGE LINES (MAIN unit)
4-5 PORT ALLOCATIONS
4-5-1 OUTPUT EXPANDER (FRONT unit; IC1)
4-5-2 OUTPUT EXPANDER (MAIN unit; IC7)
4-5-3 CPU (MAIN unit; IC20)
Description
The voltage from a DC power supply.
The same voltage as the HV line which is con-
trolled by the power switching circuit (Q23, Q24).
When the [POWER] switch is pushed, the CPU
outputs the “PWON” control signal to the power
switching circuit to turn the circuit ON.
Common 5 V for the CPU converted from the HV
line by the CPU5V regulator circuit (IC10). The
circuit outputs the voltage regardless of the
power ON/OFF condition.
Common 8 V converted from the VCC line by the
8V regulator circuit (IC9).
Common 5 V converted from the VCC line by the
5V regulator circuit (Q27, Q28).
Receive 8 V controlled by the R8 regulator circuit
(Q26, Q30, D24) using the “TXC” signal from the
CPU (IC20, pin 16).
Transmit 8 V controlled by the T8 regulator circuit
(Q25, Q29, D23) using the “TMUT” signal from
the CPU (IC20, pin 17).
Line
HV
VCC
CPU5V
8V
5V
R8V
T8V
I/O port for data signals from/to the D/A
converter (IC7).
Outputs strobe signals for the level
controller (or D/A converter) (IC6).
Output ports for LCD control signals to
the LCD driver (FRONT unit; IC1)
Outputs clock signal for the LCD driver
(FRONT unit; IC1)
Outputs data signals for the LCD driver
(FRONT unit; IC1)
Outputs strobe signals for the PLL IC
(IC4).
Outputs R8 regulator circuit (Q26, Q30,
D24) control signal.
Outputs T8 regulator circuit (Q25, Q29,
D23) control signal.
Outputs control signal for the AF regu-
lator circuit (Q39, Q40, D31).
High : While AF amplifier (IC8) is acti-
vated.
Outputs IF bandwidth control signal.
High : While IF bandwidth is narrow.
Input port for the data signals from the
DTMF decoder (IC19).
Outputs clock signal to the DTMF
decoder (IC19).
Outputs data signals to the PLL IC
(IC4), level controller (or D/A converter)
(IC6), compander IC (IC14) and option-
al board (connect to J1).
Input port for the clock signal from the
optional board via J1.
Outputs clock signal to the PLL IC
(IC4), level controller (or D/A converter)
(IC6), D/A converter (IC7), compander
IC (IC14) and optional board (connect
to J1).
Outputs chip select signal for the
optional board via J1.
Input ports for the key matrix.
Input port for the PTT switch from the
optional board via J1.
Low : External PTT switch is ON.
Input port for the microphone hanger
detection signal.
Low : Microphone on hook
Outputs BUSY detection signal for the
optional board via J1.
Input port for AF mute signal from the
optional board via J1.
1
2
8,
9
10
11
13
16
17
18
19
20
21
22
23
24
25
26–28
29
30
31
32
DSDA
DAST
LINH,
LCS
LCK
LSO
PLST
TXC
TMUT
AFON
NWC
DDSD
DDAC
SO
SI
SCK
CCS
KR2–
KR0
PTTO
HANG
BUSY
RMUT
Pin
Port
Description
number
name
4 - 4
Output tunable band pass filter control
signals.
Output port for
tunable band pass filter control signal
while receiving.
output power control signal while
transmitting.
1–3
4
T1–T3
T4
Pin
Port
Description
number
name
Output ports for key matrix.
Outputs LCD backlight control signal.
Low : While LCD backlight is dim.
Outputs LCD backlight control signal.
Low : While LCD backlight is OFF.
Outputs high-pass filter’s characteris-
tics select signal.
Outputs external device control signal.
High : When matched 2/5-tone signals
are received.
Output ports for LCD control signal.
1–3
4
5
6
7
12–55
KS0–KS2
DIM1
DIM2
FSW
HORN
SEG1–SEG40,
COM1–COM4
Pin
Port
Description
number
name
