4 - 3
4-2-4 APC CIRCUIT
The APC circuit (IC4, Q22) protects the drive and power
amplifiers from excessive current drive, and selects output
power of HIGH, LOW2 or LOW1.
The power detector circuit (D2) detects the transmit power
output level and converts it into DC voltage. The output volt-
age is at a minimum level when the antenna impedance is
matched at 50
Ω
and is increased when it is mismatched.
The detected voltage is applied to the differential amplifier
(IC4, pin 3), and the “T4” signal from the D/A converter
(IC27, pin 4), controlled by the CPU (IC14), is applied to the
other input for reference. When antenna impedance is mis-
matched, the detected voltage exceeds the power setting
voltage. Then the output voltage of the differential amplifier
(IC4, pin 4) controls the input current of the drive amplifier
(Q2) and power amplifier (Q1) to reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX/RX VCO circuit (Q12, Q11).
The oscillated signal is amplified at the buffer amplifiers (Q8,
Q7) and then applied to the PLL IC (IC1, pin 5).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the refer-
ence frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUIT
The VCO circuit contains a separate RX VCO (Q11, D6,
D40–D42) and TX VCO (Q12, D7, D8, D43–D45). The oscil-
lated signal is amplified at the buffer amplifiers (Q8, Q6) and
is then applied to the T/R switch (D5, D4). Then the receive
1st LO (Rx) signal is applied to the 1st mixer (Q19) and the
transmit (Tx) signal to the YGR amplifier circuit (Q3).
A portion of the signal from the buffer amplifier (Q8) is fed
back to the PLL IC (IC1, pin 5) via the buffer amplifier (Q7)
as the comparison signal.
• PLL circuit
Shift register
×
2
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.6 MHz
31.2 MHz signal
to the FM IF IC
8
Buffer
Q8
Buffer
Q6
Buffer
Q7
Doubler
1
2
3
SCK
SO
PLST
to transmitter circuit
to 1st mixer circuit
D4
D5
14
5
Q15
IC1 SA7025DK-T
Q12, D7, D8, D43–D45
TX VCO
Q11, D6, D40–D42
RX VCO
• APC circuit
Q1
Power
amp.
Q2
Driver
amp.
IC4
+
–
T5V
RF signal
from PLL
to antenna
T4
TMUT
Q22
S5V
APC control circuit
Power detector
circuit (D2)
D2
L5
