4 - 5
4-5 UT-103 CIRCUIT DESCRIPTION
4-5-1 GENERAL
IC1 is the FFSK modem IC which is controlled by serial data
bus line (“CCS”, “SI”, “SO”, “SCK”, “CIRQ” signals) from the
IC-F1610’s CPU. The IC is composed FFSK transmitting
and receiving circuit, data register circuits, transmitting and
receiving data buffer circuits, and so on.
X1 is oscillated 4.032 MHz reference signal to the IC1.
4-5-2 DECODEING CIRCUIT
The input signal from the J1, pin 23 (IC-F1610’s MAIN unit)
via the “DISC IN” signal is applied to the FFSK modem IC
(IC1, pin 10), and is then detected bit synchronization detec-
tion within 16 bit.
4-5-3 ENCODEING CIRCUIT
The 8 bit FFSK signal is made by serial data bus line sig-
nals, and is then output from the FFSK modem IC (IC1, pin
13).
In case of the FFSK signal is used for the PM modulation,
the FM/PM switch (IC2) is switcheded to pin 7.
In case of the FFSK signal is used for the FM modulation,
the FM/PM switch (IC2) is switched to pin 6.
The output signal from IC2, pin 1 is applied to the IC1’s
amplifier function (pin 8). The amplified signal is output from
pin 9, and is then applied to the IC22, pin 4 (IC-F1610’s
MAIN unit) as “SIG OUT” signal. The signal is amplified at
the buffer amplifier (IC-F1610’s MAIN unit; IC503, pin 3),
and is applied to the D/A convertor IC (IC-F1610’s MAIN
unit; IC5, pin 4). The signal is applied to the amplifier (IC-
F1610’s MAIN unit; Q52), and is then applied to the IC-
F1610’s modulation circuit (IC-F1610’s MAIN unit; Q23,
D21, D22, D42, D43) via the “MOD” signal.
FFSK receiving
circuit
Check sum
(generator/check circuit)
Receiving data
buffer circuit
FFSK transmitting
circuit
SYNC/SYNC
detecting circuit
SYNC programming
circuit
Address decoder
circuit
Control register
circuit
Condition register
circuit
Transmitting data
buffer circuit
Clock generator
¥ Serial bus line
interface
¥ Control logic
Data register
10
13
3
8
9
19
17
21
23
20
2
Data register
Byte counter
Interruption generator
A
A
B
C
D
E
F
G
B
C
D
E
F
G
H
I
J
K
H
I
J
K
: Receiving signal
: Clock signal
: Chip select sigal
: Reply data signal
: Serial clock signal
: Command data signal
: Wake signal
: Transmitting signal
: IRQ signal
: Amplifier input
Amp.
: Amplifier output
• UT-103 BLOCK DIAGRAM
