Icom IC-22S PLL Synthesized 2-Meter Transceiver
Instruction Manual and Service Notes
13
Reference oscillator divider
IC3 is an IC used to produce the reference frequency for the synthesizer, and includes a quartz
crystal oscillator and a 12-stage high speed divider. The oscillator produces 7.68 MHz oscillations
which the high-speed divider section divides by 1024 to give the 7.5 kHz reference pulses.
Phase detection loop filter
IC2 is a phase detector for the frequency synthesizer and is made up of a digital phase comparator
and an amplifier for the active low-pass filter. Reference pulses from 1C3 are supplied to IC2 Pin 7
and divided pulses from ICl to 1C2 Pin 8, and the digital phase comparator produces output which
is proportional to the difference in phase of these inputs, and is taken out at 1C2 Pin 3. Damping
factor of this output is set at 0.6. Lock-up time is set to 50 msec, 25% overshoot by a lag-lead
filter consisting of R9, R10, R8, C10 and the filter amplifier in 1C2.
If the divider output frequency becomes higher than the reference frequency, output voltage of the
lag-lead filter becomes low and the VCO frequency is lowered. When the divider output frequency
becomes low, circuit action is the reverse, and the VCO synchronizes the output with the reference
frequency.
Lock indication circuit, transmission termination circuit
At 1C2 Pin 4 there is a pulse output which is equal to VCC of Pin 5 when reference pulses and
divider output have the same frequency. When these inputs to 1C2 are not phase locked they have
a width proportional to the phase difference of the inputs. Pin 4 output pulses are integrated by R7,
C8, and when the integrated value obtained exceeds the junction potential of Q4, Q4 conducts and
Qi of the next stage also is turned on.
Transmission is terminated when current flowing through Dl connected to the Qi collector causes
base voltage of main unit Q32 to be lowered and the lock is released. As the transmit 9V supply
comes down, the signal lamp lights during transmission to indicate that lock-up is no longer in
effect. When Q2 base bias disappears, the meter lamp goes out both for transmit and receive and,
together with the signal lamp, indicates that lock is not present.
Ripple filter
The ripple filter, Q3, acts to further smooth the 9V supply and so protect the VCO phase
comparator and loop filter against voltage variations and improve stability.
Lock start circuit
When PLL lock is applied, the upper frequency limit is determined mainly by the operating
frequency of the divider ½ 1C6, and the VCO filter L7 is set so that oscillation is at this upper limit
when loop filter output is at maximum.
LO switching circuit
1st LO output from PLL is supplied to J1 and J2. While receiving, forward bias passes through RiO,
L43, R155, and flows through Dl5. D15 is switched on so the 1st LO is directed to L43.
Similarly, during transmit, forward current passes through R96, R155, flows through in D16, which
is switched on and 1st LO is supplied to 1C3.
