Icom IC-22S PLL Synthesized 2-Meter Transceiver
Instruction Manual and Service Notes
12
Local oscillator
The overtone oscillator in Q7 is provided to reduce spurious signals resulting from multiplication of
the fundamental oscillator. L6 is provided in series with the crystal to facilitate frequency
adjustment. L5, which is connected to the collector, is tuned to a frequency that is three (3) times
the overtone oscillator output, giving a frequency of 133.69 MHz.
Frequency converter
Balanced mixer 1C4 is a voltage regulator and a differential amplifier. A portion of the buffer
amplifier output is fed to the voltage regulator portion of 1C4 and input to the differential amplifier
is the local oscillator output. This is fed through U to balance the transformation of pulses. Using
this frequency conversion technique employing the MHz signal insures the elimination of spurious
signals in the PLL output.
Low pass
filter
The Heterodyning process in various frequencies being present at the output of ICC4, but the LPF
passes only the frequencies of 6 MHz or lower.
Limiting amplifier
Since the level of the LPF output is small, a broad band amplifier ICS consisting of 3 differential
amplifier stages is provided to amplify these signals. The interface with the divide by two circuit is
transistor Q6.
Divide by two
Since maximum operating frequency of ICI is low, ½ of 1C6, whose operating frequency is high,
divides the Q6 output frequency by 2, to give signals of approximately 3 MHz or less which are
supplied to the programmable divider.
Programmable divider
IC! divides the 1C6 output using a frequency division ratio determined by the program set by the
diode matrix.
This IC operates in binary and the maximum dividing ratio is 255. Because of this circuit’s action,
lock is not released when VCO free-running oscillations are at the upper frequency limit. At the low
frequency limit, lock-up is terminated when the frequency of the VCO is lower than a value equal to
the local oscillator frequency plus N times the reference frequencies. When power is connected, the
transient voltage of the differentiating circuit defined by C24, R2 is passed through D2, and
potential at the varicap diode temporarily goes to a high value. As this voltage falls, and the value
set by the programmable divider N is entered, D2 is reverse-biased, and in normal conditions is off.
By putting D4 in parallel to R12 the charge on C4 is discharged quickly when power is switched off,
and when power is connected again the lock circuit is reset.
Diode Matrix
This is a binary code, read only memory, defining a frequency as a binary number. This matrix
determines the frequency dividing ratio (N) to be employed by the programmable divider in order
to obtain the frequency required in response to activation of each of the 22 switch positions.
See diode matrix charts
