IBT Technologies IB880, User Manual

Page: 44 / 65

BIOS SETUP
40 IB880 User’s Manual
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate
its charge before the SDRAM refreshes. The default setting for the
Active to Precharge Delay is
3 .
DRAM Data Integrity Mode
Select ECC if your memory module supports it. The memory controller
will detect and correct single-bit soft memory errors. The memory
controller will also be able to detect double-bit errors though it will not
be able to correct them. This provides increased data integrity and
system stability.
MGM Core Frequency
This field sets the frequency of the DRAM memory installed. The
default setting is
Auto Max 266MHz .
System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if
any program writes to this memory area, a system error may result.
Video BIOS Cacheable
The Setting Enabled allows caching of the video BIOS ROM at
C0000h-F7FFFh, resulting in better video performance. However, if
any program writes to this memory area, a system error may result.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory
space below 16 MB. The choices are
Enabled and Disabled .
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Delay Prior to Thermal
This field activates the CPU thermal function after the systems boots for
the set number of minutes. The options are
16Min and 64Min .