Chapter 1. Architecture and technical description
23
A diagram showing the Power S822LC server buses and logical architecture is shown in
Figure 1-13.
Figure 1-13 Power S822LC server buses and logical architecture
Each processor has 32 PCIs lanes split into three channels: two channels are PCIe Gen3 x8
and one channel is PCIe Gen 3 x16.
The PCIe channels are connected to the PCIe slots, which can support GPUs and other
high-performance adapters, such as InfiniBand.
Table 1-8 lists the total I/O bandwidth of a Power S822LC server.
Table 1-8 I/O bandwidth
For the PCIe Interconnect, each POWER8 processor has 32 PCIe lanes running at 9.6 Gbps
full-duplex. The bandwidth formula is calculated as follows:
Thirty-two lanes * 2 processors * 9.6 Gbps * 2 = 128 GBps
I/O
I/O bandwidth (maximum theoretical)
Total I/O bandwidth
64 GBps simplex
128 GBps duplex
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Summary of Contents for S822LC
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