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Application Note

(Includes Differences for 970FX to 970MP)

Preliminary

IBM PowerPC

®

970MP RISC Microprocessor

AppNote_970FX-MP_Differences_LOF.fm.1.0
November 15, 2006

Page 5 of 25

Figure 5-1.

Dual Cores sharing processor interface ................................................................................. 11

Figure 5-2.

970MP Power Modes ............................................................................................................. 17

Figure 8-1.

PowerPC 970MP Mechanical Package (Side and Top View) ................................................ 23

Figure 8-2.

PowerPC 970MP Bottom Surface of CBGA Package (Bottom View) .................................... 24

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Summary of Contents for POWERPC 970MP

Page 1: ...IBM PowerPC 970MP RISC Microprocessor Application Note PowerPC 970MP Differences Includes Differences for 970FX to 970MP Version 1 0 Preliminary November 15 2006 ...

Page 2: ...press or implied license or indemnity under the intellectual property rights of IBM or third parties All information contained in this document was obtained in specific environments and is presented as an illustration The results obtained in other operating environments may vary While the information contained herein is believed to be accurate such information is advance and should not be relied u...

Page 3: ... 2 Transmitter Electrical Shorts Test EST 13 5 2 2 3 Receiver Electrical Shorts Test REST 14 5 2 2 4 Receiver Random Data Self Test 15 5 2 3 Bus Configuration 15 5 3 PowerTuning 17 5 3 1 Power Modes 17 5 3 2 Time Base and Decrementer 18 5 4 I2 C Bus Interface 18 5 4 1 Clock Dithering New feature for 970FX DD3 0 enhanced in 970MP 18 5 4 2 Programmable Delays for Power Saving Mode Transitions 19 5 5...

Page 4: ...Application Note Includes Differences for 970FX to 970MP IBM PowerPC 970MP RISC Microprocessor Preliminary Page 4 of 25 AppNote_970FX MP_Differences_TOC fm 1 0 November 15 2006 ...

Page 5: ...rocessor AppNote_970FX MP_Differences_LOF fm 1 0 November 15 2006 Page 5 of 25 Figure 5 1 Dual Cores sharing processor interface 11 Figure 5 2 970MP Power Modes 17 Figure 8 1 PowerPC 970MP Mechanical Package Side and Top View 23 Figure 8 2 PowerPC 970MP Bottom Surface of CBGA Package Bottom View 24 ...

Page 6: ...Application Note Includes Differences for 970FX to 970MP IBM PowerPC 970MP RISC Microprocessor Preliminary Page 6 of 25 AppNote_970FX MP_Differences_LOF fm 1 0 November 15 2006 ...

Page 7: ...9 Table 4 1 General Parameters of the PowerPC 970FX and 970MP 10 Table 5 1 PowerPC 970MP Programmable Delay Parameters 16 Table 5 2 Power Mode States 18 Table 5 3 PowerPC 970MP Latency of Deep Nap to Run Transition Full Frequency Cycles 19 Table 8 1 PowerPC 970FX and 970MP Die Size and Dimensions 20 Table 8 2 970FX Pins Duplicated for each 970MP Processing Unit 21 Table 8 3 New 970MP Pins 21 Table...

Page 8: ...Application Note Includes Differences for 970FX to 970MP IBM PowerPC 970MP RISC Microprocessor Preliminary Page 8 of 25 AppNote_970FX MP_Differences_LOT fm 1 0 November 15 2006 ...

Page 9: ...rocessors that are based on the PowerPC Architecture This dual microprocessor also called the 970MP includes a Vector SIMD facility in each core which supports high bandwidth data processing and compute intensive operations The 970MP is designed to support multiple system organizations including desktop and low end server applications up through 4 way SMP configurations The differences between the...

Page 10: ...e within the delta specified in the IBM PowerPC 970MP RISC Microprocessor Datasheet when the two processors are running Also the core frequencies will always be the same This would be true for two separate cores except for the Deep Nap case where one of two separate processors could reduce frequency to 1 64 while the other ran at functional speed The two 970MP cores must go into and come out of De...

Page 11: ...e bus header packets for each processor are queued at the arbiter Finally snoop responses from the two processors are combined on chip and sent as a single response over the PI bus to the bridge chip as indicated in the lower left corner of Figure 5 1 The additional logic at the PI BIU interface requires a SNOOPLAT and SNOOPACC value that is larger than for the 970FX but still within the programma...

Page 12: ...s the cache array size and capacity from 970FX with a corresponding doubling in size of the two copies of the L2 tag arrays Like the 970FX it is an 8 way set associative cache of 128 B lines but now consists of 1024 sets The latency for L1 misses that hit in the L2 is increased by two processor cycles in the 970MP due to the longer path from the core to the larger L2 array This load use penalty fo...

Page 13: ...red with that in the 970FX In the 970MP the windage field is used to add a fixed amount of delay to all bits prior to IAP learning in order to avoid an underflow when a guardbanding procedure is performed at the end of the IAP 5 2 2 Test Modes Two new test modes are supported for bringup of the PI interface These are the electrical shorts test EST and the pseudo random data test RDT The following ...

Page 14: ...ld on a given channel for 16 bit times after which the data value for that channel is returned to the data value of the field and the walking value is applied to the next channel for 16 bit times The process is continued until all channels have been tested Each channel is independently forced to a 1 while the field is 0 Each time a channel is tested by applying a data 1 the receiver checks to see ...

Page 15: ...st fails If the expected results are not observed on any channel an error is flagged in the status register The DIAG_RDT vector out of the receiver provides observability of any channel which did not contain expected values for the duration of the test Unlike the shorts test previously described the status register will never indicate completion of the test as there is no predefined end to the ran...

Page 16: ...d for each of these parameters for the 970MP is In addition the definitions of STATLAT SNOOPLAT and SNOOPACC in 970MP have changed due to addi tional staging of bus signals internally Thus setting a STATLAT value of 24 in the register corresponds to a delay of 22 bus beats between the last beat of the ADO packet and the first beat of the transfer handshake packet Similarly a value two larger than ...

Page 17: ...cility on the 970MP are indicated by the nodes S1 through S12 in Figure 5 2 The state diagram in Figure 5 2 represents two changes for the 970MP design First the Deep Nap state can be reached from the Nap state at any frequency Second frequency scaling between full and quarter frequency can be done directly Figure 5 2 970MP Power Modes High Speed Medium Speed Low Speed Deep Nap Doze Nap Run S1 S2 ...

Page 18: ...the time base decrementer may be increased decreased by more than one at a time Therefore testing that the decrementer has reached the value of zero in order to generate an internal interrupt is not sufficient The logic detects that the counter has wrapped around Additionally the time resolution of the counters is limited by the mesh clock frequency 5 4 I2C Bus Interface 5 4 1 Clock Dithering New ...

Page 19: ... 970 design implements dynamic power management DPM the gating of clocks to idle circuits while in an operational mode For example clocks in the pipelined vector processing units VPUs are gated on a stage by stage basis as instructions flow through the pipeline The 970FX design implements additional dynamic power management in the STS IDU and RAS units The 970MP design implements additional dynami...

Page 20: ...the PowerPC microprocessors designs Timings for each of the IBM PowerPC microprocessor family of products are located within their specific electrical specification referred to as the Datasheet Contact your IBM Sales or technical support group for the PowerPC 970MP RISC Microproces sor Datasheet 8 Package 8 1 Design Considerations for a 970MP Thermal Solution The 970MP package differs from the 970...

Page 21: ...d 970FX pins one per core on the PowerPC 970MP Table 8 3 lists the new PowerPC 970MP pins Table 8 4 lists 970FX pins not found on PowerPC 970MP Table 8 2 970FX Pins Duplicated for each 970MP Processing Unit 970FX 970MP Core0 970MP Core1 Function HRESET_B CP0_HRESET_B CP1_HRESET_B Hard Reset SRESET_B CP0_SRESET_B CP1_SRESET_B Soft Reset INT_B CP0_INT_B CP1_INT_B External Interrupt QACK_B CP0_QACK_B...

Page 22: ... 970MP package Figure 8 1 shows the side and top views of the Pb reduced package including the height from the top of the die to the bottom of the solder balls Figure 8 2 shows a bottom view of the PowerPC 970MP package Table 8 4 Deleted 970FX Pins not found on 970MP 970FX Pin 970FX Function PROCID2 Least significant bit in the 3 bit processor ID automatically set on PowerPC 970MP THERM_INT_B Dedi...

Page 23: ... specified part is symmetrical about centerlines defined by DATUMs A and B 4 Where not otherwise defined centerlines indicated are to be interpreted as a datum frame work established by DATUMS D A and B respectively This line defines the approximate boundary configuration of encapsulant as dispensed For underfill requirements see IBM Engineering Specification 71X8781 Module Encapsulation Specifica...

Page 24: ...ess otherwise specified part is symmetrical about centerlines defined by DATUMs A and B 4 Where not otherwise defined centerlines indicated are to be interpreted as a datum frame work established by DATUM D A and B respectively This line defines the approximate boundary configuration of encapsulant as dispensed For underfill requirements see IBM Engineering Specification 71X8781 Module Encapsulati...

Page 25: ...fferences for 970FX to 970MP Preliminary IBM PowerPC 970MP RISC Microprocessor Rev_Log fm 1 0 November 15 2006 Revision Log Page 25 of 25 Revision Log Revision Modification November 15 2006 Version 1 0 Initial preliminary version ...

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