Two PCIe3 switches in the system backplane provide PCIe3 buses from the system processor modules
that provide connectivity to the following features:
Note: PCIe3 switch 1 and switch 2 provide PCIe buses from processor module SCM0.
• PCIe slots
• PCIe local area network (LAN) controller
• PCIe3 internal SAS controller
The two PCIe3 switches are as follows:
Table 3 on page 2 lists the features provided by the PCIe3 switches.
Table 3. PCIe3 switches in the system.
Features provided
Switch 1 and switch 2
Lanes and ports
48-lane, 12-ports, PCIe3
With integrated 8.0 gigatransfers per second (GT/s)
Serializer/Deserializer (SerDes) speed negotiation for
each port
Lane and polarity reversal
Supported
All ports support concurrent maintenance through I2C
bus.
Yes
End-to-end cyclic redundancy check (CRC) and poison
bit error checking
Supported
Data path parity
Supported
Memory error correction
Supported
Advanced error reporting
Supported
Aggregate full duplex bandwidth
768 GT/s
Designate any port as the upstream port
Yes
27x27 mm, 676-pin FCBGA package
Yes
Power consumption
• Nominal: 8 watts
• Maximum: 12 watts
Notes:
• Up to three adapters can be in SR-IOV shared mode.
• Of the three adapters in SR-IOV shared mode, a maximum of two adapters can be either FC EC2S or EC2U.
Figure 1 on page 3 shows the rear view of the system with the location codes for the PCIe adapter
slots.
Table 4 on page 3 lists the PCIe adapter slot locations and details for the 9009-41A, 9009-42A, and
9223-42H systems.
2 Power Systems: PCIe adapter placement for the 9009-41A, 9009-42A, or 9223-42H
