4405ch02 Architecture and technical overview.fm
Draft Document for Review May 28, 2009 1:59 pm
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IBM Power 570 Technical Overview and Introduction
sees a single shared memory resource. They are interfaced to 12 memory slots, where as
each memory DIMM has its own memory buffer chip and are interfaced in a point-to-point
connection.
I/O connects to the 570 processor module using the GX+ bus. The processor module
provides a single GX+ bus. The GX+ bus provides an interface to I/O devices through the
RIO-2 connections or a 12X Channel attach connections.
2.3.1 Processor drawer interconnect cables
In combined systems that are made of more than one 570 building block, the connection
between processor cards in different building blocks is provided with a processor drawer
interconnect cable. Different processor drawer interconnect cables are required for the
different numbers of 570 building blocks that a combined system can be made of, as shown in
Figure 2-4.
Because of the redundancy and fault recovery built-in to the system interconnects, a drawer
failure does not represent a system failure. Once a problem is isolated and repaired, a system
reboot may be required to reestablish full bus speed, if the failure was specific to the
interconnects.
The SMP fabric bus that connects the processors of separate 570 building blocks is routed on
the interconnect cable that is routed external to the building blocks. The flexible cable
attaches directly to the processor cards, at the front of the 570 building block, and is routed
behind the front covers (bezels) of the 570 building blocks. There is an optimized cable for
each drawer configuration. Figure 2-4 illustrates the logical fabric bus connections between
the drawers, and shows the additional space required left of the bezels for rack installation.
Figure 2-4 Logical 570 building block connection
2.3.2 Processor clock rate
The 570 system features base 2-core, 4-core, 8-core, 12-core, and 16-core configurations
with the POWER6 processor running at 3.5 GHz, 4.2 GHz, and 4.7 GHz.